| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-03-17 | Rearrange cores. | Paul Selkirk | |
| 2014-11-18 | i2c_device_addr as output | Paul Selkirk | |
| 2014-09-11 | correct size of I2C FSM state values | Paul Selkirk | |
| When adding new I2C states, I neglected to update the size of all the state parameter values, so e.g. I2C_WAITSTOP = 14'b1 << 15; This overflows to 0, which manifests as the I2C bus hanging when asked to access an unsupported device address. | |||
| 2014-09-03 | fix i2c read buffer overrun | Paul Selkirk | |
| If a client requests data beyond the end of the coretest response, i2c_core could wait forever for txd_syn to be asserted, locking up the system. The current solution is to assume that data will be available by the time the client sends the READ_CMD and then issues the i2c read request; if no data is available, i2c_core returns 0x00. Given the relative speeds of the i2c bus and the FPGA, this seems justifiable, but it could use more scrutiny. | |||
| 2014-08-28 | initial commit of I2C code for coretest | Paul Selkirk | |
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index : core/comm/i2c | |
| An I2C slave implemented in Verilog | git repositories |
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