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authorPaul Selkirk <pselkirk@isc.org>2014-09-11 13:56:42 -0400
committerPaul Selkirk <pselkirk@isc.org>2014-09-11 13:56:42 -0400
commit595a3e72b4e2c166cc978e59c025560353df0a6b (patch)
tree325fbbc0988f754786c6a8d49049616196e72c4f
parenta768072bbe3ea9762ee3325ffb5c42c3156e7859 (diff)
correct size of I2C FSM state values
When adding new I2C states, I neglected to update the size of all the state parameter values, so e.g. I2C_WAITSTOP = 14'b1 << 15; This overflows to 0, which manifests as the I2C bus hanging when asked to access an unsupported device address.
-rw-r--r--src/rtl/i2c_core.v49
1 files changed, 22 insertions, 27 deletions
diff --git a/src/rtl/i2c_core.v b/src/rtl/i2c_core.v
index a026545..f5d7c87 100644
--- a/src/rtl/i2c_core.v
+++ b/src/rtl/i2c_core.v
@@ -80,22 +80,22 @@ module i2c_core (
////////////////
///// protocol-level state machine
////////////////
- parameter I2C_START = 14'b1 << 0; // should only pass through this state for one cycle
- parameter I2C_RESTART = 14'b1 << 1;
- parameter I2C_DADDR = 14'b1 << 2;
- parameter I2C_ACK_DADDR = 14'b1 << 3;
- parameter I2C_WR_DATA = 14'b1 << 4;
- parameter I2C_RXD_SYN = 14'b1 << 5;
- parameter I2C_RXD_ACK = 14'b1 << 6;
- parameter I2C_ACK_WR = 14'b1 << 7;
- parameter I2C_END_WR = 14'b1 << 8;
- parameter I2C_TXD_SYN = 14'b1 << 9;
- parameter I2C_TXD_ACK = 14'b1 << 10;
- parameter I2C_RD_DATA = 14'b1 << 11;
- parameter I2C_ACK_RD = 14'b1 << 12;
- parameter I2C_END_RD = 14'b1 << 13;
- parameter I2C_END_RD2 = 14'b1 << 14;
- parameter I2C_WAITSTOP = 14'b1 << 15;
+ parameter I2C_START = 16'b1 << 0; // should only pass through this state for one cycle
+ parameter I2C_RESTART = 16'b1 << 1;
+ parameter I2C_DADDR = 16'b1 << 2;
+ parameter I2C_ACK_DADDR = 16'b1 << 3;
+ parameter I2C_WR_DATA = 16'b1 << 4;
+ parameter I2C_ACK_WR = 16'b1 << 5;
+ parameter I2C_END_WR = 16'b1 << 6;
+ parameter I2C_RD_DATA = 16'b1 << 7;
+ parameter I2C_ACK_RD = 16'b1 << 8;
+ parameter I2C_END_RD = 16'b1 << 9;
+ parameter I2C_END_RD2 = 16'b1 << 10;
+ parameter I2C_WAITSTOP = 16'b1 << 11;
+ parameter I2C_RXD_SYN = 16'b1 << 12;
+ parameter I2C_RXD_ACK = 16'b1 << 13;
+ parameter I2C_TXD_SYN = 16'b1 << 14;
+ parameter I2C_TXD_ACK = 16'b1 << 15;
parameter I2C_nSTATES = 16;
@@ -304,9 +304,7 @@ module i2c_core (
end
I2C_RXD_ACK: begin // wait for coretest ack
if (rxd_ack)
- begin
- rxd_syn_reg <= 0;
- end
+ rxd_syn_reg <= 0;
end
I2C_ACK_WR: begin
SDA_pd <= 1'b1; // active pull down ACK
@@ -325,17 +323,14 @@ module i2c_core (
// read branch
I2C_TXD_SYN: begin // get data from the coretest bus
- if (txd_syn)
- begin
- I2C_rdata <= txd_data;
- txd_ack_reg <= 1;
- end
+ if (txd_syn) begin
+ I2C_rdata <= txd_data;
+ txd_ack_reg <= 1;
+ end
end
I2C_TXD_ACK: begin // send coretest ack
if (!txd_syn)
- begin
- txd_ack_reg <= 0;
- end
+ txd_ack_reg <= 0;
end
I2C_RD_DATA: begin // shift out data on falling edges of clock
SDA_pd <= I2C_rdata[7] ? 1'b0 : 1'b1;