diff options
| author | Paul Selkirk <paul@psgd.org> | 2015-10-31 22:38:53 -0400 |
|---|---|---|
| committer | Paul Selkirk <paul@psgd.org> | 2015-10-31 22:38:53 -0400 |
| commit | 2f11ecd913368bf955aed40d22901b9f4998e8cc (patch) | |
| tree | e82b5bb51eae4e4ec34070e4a5041e13bc3c221d | |
| parent | fb17b78136c9e3efe54ac55ab08086256b3a0944 (diff) | |
2-cycle sys_req delay for modexps6, because block RAMs
| -rw-r--r-- | src/rtl/fmc_arbiter_cdc.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/rtl/fmc_arbiter_cdc.v b/src/rtl/fmc_arbiter_cdc.v index 0eca0b1..63e65b5 100644 --- a/src/rtl/fmc_arbiter_cdc.v +++ b/src/rtl/fmc_arbiter_cdc.v @@ -113,12 +113,12 @@ module fmc_arbiter_cdc # // - // System Request 1-cycle delay to compensate registered mux delay in user-side logic + // System Request 2-cycle delay to compensate registered mux delay in user-side logic // - reg sys_req_dly = 1'b0; + reg [ 1: 0] sys_req_dly = 2'b00; always @(posedge sys_clk) - sys_req_dly <= sys_req; + sys_req_dly <= {sys_req_dly[0], sys_req}; // // SYS_CLK -> FMC_CLK Acknowledge @@ -131,7 +131,7 @@ module fmc_arbiter_cdc # ( .src_clk(sys_clk), .src_din(sys_data_in), - .src_req(sys_req_dly), + .src_req(sys_req_dly[1]), .dst_clk(fmc_clk), .dst_dout(fmc_dout), |