| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-08-23 | (1) Updated qr interface to include clock and reset needed for internal ↵ | Joachim Strömbergson | |
| pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support. | |||
| 2016-12-28 | (1) Cleanup of top an core code with no functional changes. The code is now ↵cleanup | Joachim Strömbergson | |
| much more compact. (2) Fixed how the QR modules are used in parallel to actually work in parallel. This increases performance. (3) Changed registers into arrays and cleaned up how operands and data are accessed. This decreased total design size. | |||
| 2015-04-30 | (1) Added api addresses and constants for core name and version. (2) Changed ↵ | Joachim Strömbergson | |
| addresses for control, status and config to match the ct standard. (3) Updated the testbench to use the changed addresses. | |||
| 2014-09-03 | Adding testbenches for core and top. | Joachim Strömbergson | |
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index : core/cipher/chacha | |
| Verilog 2001 implementation of the ChaCha stream cipher | git repositories |
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