| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-30 | Adding two more pipeline registers in the qr module. Added two more wait cycles. | Joachim Strömbergson |
| 2018-08-23 | Debugged pipeline register and state update. All test cases ok.timing_fix | Joachim Strömbergson |
| 2018-08-23 | (1) Adding pipeline register update code and a set of pipeline registers. Reg... | Joachim Strömbergson |
| 2018-08-23 | (1) Updated qr interface to include clock and reset needed for internal pipel... | Joachim Strömbergson |
| 2016-12-28 | (1) Cleanup of top an core code with no functional changes. The code is now m...cleanup | Joachim Strömbergson |
| 2015-04-30 | (1) Added api addresses and constants for core name and version. (2) Changed ... | Joachim Strömbergson |
| 2014-11-06 | Fixes to nits found using the verilator linter. | Joachim Strömbergson |
| 2014-09-26 | Update of ChaCha with fixes found during synthesis. | Joachim Strömbergson |
| 2014-09-03 | Adding RTL code for the ChaCha stream cipher. | Joachim Strömbergson |
 |
index : core/cipher/chacha | |
| Verilog 2001 implementation of the ChaCha stream cipher | git repositories |
| aboutsummaryrefslogtreecommitdiff |