| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-08-23 | Debugged pipeline register and state update. All test cases ok.timing_fix | Joachim Strömbergson | |
| 2018-08-23 | (1) Adding pipeline register update code and a set of pipeline registers. ↵ | Joachim Strömbergson | |
| Registers are not connected at the this stage. (2) Added self testing tetst cases and debug outputs to observe internal behaviour. | |||
| 2018-08-23 | (1) Updated qr interface to include clock and reset needed for internal ↵ | Joachim Strömbergson | |
| pipeline registers. (2) Added testbench for the qr module. (3) Added qr simulation target. (4) Added lint support. | |||
| 2014-11-06 | Fixes to nits found using the verilator linter. | Joachim Strömbergson | |
| 2014-09-03 | Adding RTL code for the ChaCha stream cipher. | Joachim Strömbergson | |
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index : core/cipher/chacha | |
| Verilog 2001 implementation of the ChaCha stream cipher | git repositories |
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