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-rw-r--r--src/tb/tb_chacha.v258
1 files changed, 140 insertions, 118 deletions
diff --git a/src/tb/tb_chacha.v b/src/tb/tb_chacha.v
index ac2d3b0..fab2ad7 100644
--- a/src/tb/tb_chacha.v
+++ b/src/tb/tb_chacha.v
@@ -36,19 +36,15 @@
//
//======================================================================
-//------------------------------------------------------------------
-// Simulator directives.
-//------------------------------------------------------------------
-`timescale 1ns/100ps
-
module tb_chacha();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- localparam DEBUG = 0;
+ localparam DEBUG = 1;
- localparam CLK_HALF_PERIOD = 2;
+ localparam CLK_HALF_PERIOD = 1;
+ localparam CLK_PERIOD = 2 * CLK_HALF_PERIOD;
localparam TC1 = 1;
localparam TC2 = 2;
@@ -111,20 +107,6 @@ module tb_chacha();
localparam ADDR_IV1 = 8'h21;
localparam ADDR_DATA_IN0 = 8'h40;
- localparam ADDR_DATA_IN1 = 8'h41;
- localparam ADDR_DATA_IN2 = 8'h42;
- localparam ADDR_DATA_IN3 = 8'h43;
- localparam ADDR_DATA_IN4 = 8'h44;
- localparam ADDR_DATA_IN5 = 8'h45;
- localparam ADDR_DATA_IN6 = 8'h46;
- localparam ADDR_DATA_IN7 = 8'h47;
- localparam ADDR_DATA_IN8 = 8'h48;
- localparam ADDR_DATA_IN9 = 8'h49;
- localparam ADDR_DATA_IN10 = 8'h4a;
- localparam ADDR_DATA_IN11 = 8'h4b;
- localparam ADDR_DATA_IN12 = 8'h4c;
- localparam ADDR_DATA_IN13 = 8'h4d;
- localparam ADDR_DATA_IN14 = 8'h4e;
localparam ADDR_DATA_IN15 = 8'h4f;
localparam ADDR_DATA_OUT0 = 8'h80;
@@ -170,25 +152,20 @@ module tb_chacha();
reg display_cycle_ctr;
reg display_read_write;
+ reg display_core_state;
//----------------------------------------------------------------
// Chacha device under test.
//----------------------------------------------------------------
chacha dut(
- // Clock and reset.
.clk(tb_clk),
.reset_n(tb_reset_n),
-
- // Control.
.cs(tb_cs),
.we(tb_write_read),
-
- // Data ports.
.address(tb_address),
.write_data(tb_data_in),
- .read_data(tb_data_out),
- .error(tb_error)
+ .read_data(tb_data_out)
);
@@ -218,6 +195,24 @@ module tb_chacha();
$display("cycle = %016x:", cycle_ctr);
end
+ if (display_core_state)
+ begin
+ $display("core ctrl: 0x%02x, core_qr_ctr: 0x%02x, core_dr_ctr: 0x%02x, init: 0x%01x, next: 0x%01x, core_ready: 0x%02x",
+ dut.core.chacha_ctrl_reg, dut.core.qr_ctr_reg,
+ dut.core.dr_ctr_reg, dut.core.init,
+ dut.core.next, dut.core.ready_reg);
+
+ $display("state0_reg = 0x%08x, state1_reg = 0x%08x, state2_reg = 0x%08x, state3_reg = 0x%08x",
+ dut.core.state_reg[00], dut.core.state_reg[01], dut.core.state_reg[02], dut.core.state_reg[03]);
+ $display("state4_reg = 0x%08x, state5_reg = 0x%08x, state6_reg = 0x%08x, state7_reg = 0x%08x",
+ dut.core.state_reg[04], dut.core.state_reg[05], dut.core.state_reg[06], dut.core.state_reg[07]);
+ $display("state8_reg = 0x%08x, state9_reg = 0x%08x, state10_reg = 0x%08x, state11_reg = 0x%08x",
+ dut.core.state_reg[08], dut.core.state_reg[09], dut.core.state_reg[10], dut.core.state_reg[11]);
+ $display("state12_reg = 0x%08x, state13_reg = 0x%08x, state14_reg = 0x%08x, state15_reg = 0x%08x",
+ dut.core.state_reg[12], dut.core.state_reg[13], dut.core.state_reg[14], dut.core.state_reg[15]);
+ $display("");
+ end
+
if (display_read_write)
begin
@@ -238,31 +233,39 @@ module tb_chacha();
//----------------------------------------------------------------
- // set_display_prefs()
- //
- // Set the different monitor displays we want to see during
- // simulation.
+ // reset_dut
//----------------------------------------------------------------
- task set_display_prefs(
- input cycles,
- input read_write);
+ task reset_dut;
begin
- display_cycle_ctr = cycles;
- display_read_write = read_write;
+ tb_reset_n = 0;
+ #(2 * CLK_PERIOD);
+ tb_reset_n = 1;
end
- endtask // set_display_prefs
+ endtask // reset_dut
//----------------------------------------------------------------
- // reset_dut
+ // init_sim()
+ //
+ // Set the input to the DUT to defined values.
//----------------------------------------------------------------
- task reset_dut();
+ task init_sim;
begin
- tb_reset_n = 0;
- #(4 * CLK_HALF_PERIOD);
- tb_reset_n = 1;
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+ tb_clk = 0;
+ tb_reset_n = 0;
+ tb_cs = 0;
+ tb_write_read = 0;
+ tb_address = 8'h0;
+ tb_data_in = 32'h0;
+
+ display_cycle_ctr = 0;
+ display_read_write = 0;
+ display_core_state = 0;
end
- endtask // reset_dut
+ endtask // init_sim
//----------------------------------------------------------------
@@ -276,11 +279,11 @@ module tb_chacha();
tb_cs = 1;
tb_write_read = 0;
tb_address = addr;
- #(2 * CLK_HALF_PERIOD);
+ #(CLK_PERIOD);
tb_cs = 0;
tb_write_read = 0;
- tb_address = 8'h00;
- tb_data_in = 32'h00000000;
+ tb_address = 8'h0;
+ tb_data_in = 32'h0;
end
endtask // read_reg
@@ -296,11 +299,11 @@ module tb_chacha();
tb_write_read = 1;
tb_address = addr;
tb_data_in = data;
- #(2 * CLK_HALF_PERIOD);
+ #(CLK_PERIOD);
tb_cs = 0;
tb_write_read = 0;
- tb_address = 8'h00;
- tb_data_in = 32'h00000000;
+ tb_address = 8'h0;
+ tb_data_in = 32'h0;
end
endtask // write_reg
@@ -310,36 +313,49 @@ module tb_chacha();
//
// Dump the internal state of the top to std out.
//----------------------------------------------------------------
- task dump_top_state();
+ task dump_top_state;
begin
$display("");
$display("Top internal state");
$display("------------------");
$display("init_reg = %01x", dut.init_reg);
$display("next_reg = %01x", dut.next_reg);
- $display("ready_reg = %01x", dut.ready_reg);
$display("keylen_reg = %01x", dut.keylen_reg);
$display("rounds_reg = %01x", dut.rounds_reg);
$display("");
- $display("key0_reg = %08x, key1_reg = %08x, key2_reg = %08x, key3_reg = %08x", dut.key0_reg, dut.key1_reg, dut.key2_reg, dut.key3_reg);
- $display("key4_reg = %08x, key5_reg = %08x, key6_reg = %08x, key7_reg = %08x", dut.key4_reg, dut.key5_reg, dut.key6_reg, dut.key7_reg);
+ $display("key0_reg = %08x, key1_reg = %08x, key2_reg = %08x, key3_reg = %08x",
+ dut.key_reg[0], dut.key_reg[1], dut.key_reg[2], dut.key_reg[3]);
+ $display("key4_reg = %08x, key5_reg = %08x, key6_reg = %08x, key7_reg = %08x",
+ dut.key_reg[4], dut.key_reg[5], dut.key_reg[6], dut.key_reg[7]);
$display("");
- $display("iv0_reg = %08x, iv1_reg = %08x", dut.iv0_reg, dut.iv1_reg);
+ $display("iv0_reg = %08x, iv1_reg = %08x", dut.iv_reg[0], dut.iv_reg[1]);
$display("");
- $display("data_in0_reg = %08x, data_in1_reg = %08x, data_in2_reg = %08x, data_in3_reg = %08x", dut.data_in0_reg, dut.data_in1_reg, dut.data_in2_reg, dut.data_in3_reg);
- $display("data_in4_reg = %08x, data_in5_reg = %08x, data_in6_reg = %08x, data_in7_reg = %08x", dut.data_in4_reg, dut.data_in5_reg, dut.data_in6_reg, dut.data_in7_reg);
- $display("data_in8_reg = %08x, data_in9_reg = %08x, data_in10_reg = %08x, data_in11_reg = %08x", dut.data_in8_reg, dut.data_in9_reg, dut.data_in10_reg, dut.data_in11_reg);
- $display("data_in12_reg = %08x, data_in13_reg = %08x, data_in14_reg = %08x, data_in15_reg = %08x", dut.data_in12_reg, dut.data_in13_reg, dut.data_in14_reg, dut.data_in15_reg);
+ $display("data_in0_reg = %08x, data_in1_reg = %08x, data_in2_reg = %08x, data_in3_reg = %08x",
+ dut.data_in_reg[00], dut.data_in_reg[01], dut.data_in_reg[02], dut.data_in_reg[03]);
+ $display("data_in4_reg = %08x, data_in5_reg = %08x, data_in6_reg = %08x, data_in7_reg = %08x",
+ dut.data_in_reg[04], dut.data_in_reg[05], dut.data_in_reg[06], dut.data_in_reg[07]);
+ $display("data_in8_reg = %08x, data_in9_reg = %08x, data_in10_reg = %08x, data_in11_reg = %08x",
+ dut.data_in_reg[08], dut.data_in_reg[09], dut.data_in_reg[10], dut.data_in_reg[11]);
+ $display("data_in12_reg = %08x, data_in13_reg = %08x, data_in14_reg = %08x, data_in15_reg = %08x",
+ dut.data_in_reg[12], dut.data_in_reg[13], dut.data_in_reg[14], dut.data_in_reg[15]);
$display("");
- $display("data_out_valid_reg = %01x", dut.data_out_valid_reg);
- $display("data_out0_reg = %08x, data_out1_reg = %08x, data_out2_reg = %08x, data_out3_reg = %08x", dut.data_out0_reg, dut.data_out1_reg, dut.data_out2_reg, dut.data_out3_reg);
- $display("data_out4_reg = %08x, data_out5_reg = %08x, data_out6_reg = %08x, data_out7_reg = %08x", dut.data_out4_reg, dut.data_out5_reg, dut.data_out6_reg, dut.data_out7_reg);
- $display("data_out8_reg = %08x, data_out9_reg = %08x, data_out10_reg = %08x, data_out11_reg = %08x", dut.data_out8_reg, dut.data_out9_reg, dut.data_out10_reg, dut.data_out11_reg);
- $display("data_out12_reg = %08x, data_out13_reg = %08x, data_out14_reg = %08x, data_out15_reg = %08x", dut.data_out12_reg, dut.data_out13_reg, dut.data_out14_reg, dut.data_out15_reg);
+ $display("ready = 0x%01x, data_out_valid = %01x", dut.core_ready, dut.core_data_out_valid);
+ $display("data_out00 = %08x, data_out01 = %08x, data_out02 = %08x, data_out03 = %08x",
+ dut.core_data_out[511 : 480], dut.core_data_out[479 : 448],
+ dut.core_data_out[447 : 416], dut.core_data_out[415 : 384]);
+ $display("data_out04 = %08x, data_out05 = %08x, data_out06 = %08x, data_out07 = %08x",
+ dut.core_data_out[383 : 352], dut.core_data_out[351 : 320],
+ dut.core_data_out[319 : 288], dut.core_data_out[287 : 256]);
+ $display("data_out08 = %08x, data_out09 = %08x, data_out10 = %08x, data_out11 = %08x",
+ dut.core_data_out[255 : 224], dut.core_data_out[223 : 192],
+ dut.core_data_out[191 : 160], dut.core_data_out[159 : 128]);
+ $display("data_out12 = %08x, data_out13 = %08x, data_out14 = %08x, data_out15 = %08x",
+ dut.core_data_out[127 : 96], dut.core_data_out[95 : 64],
+ dut.core_data_out[63 : 32], dut.core_data_out[31 : 0]);
$display("");
end
endtask // dump_top_state
@@ -350,27 +366,23 @@ module tb_chacha();
//
// Dump the internal state of the core to std out.
//----------------------------------------------------------------
- task dump_core_state();
+ task dump_core_state;
begin
$display("");
$display("Core internal state");
$display("-------------------");
-// $display("Internal data state vector:");
-// $display("0x%064x", dut.core.state_reg);
- $display("");
-
- $display("Round state X:");
- $display("x0_reg = %08x, x1_reg = %08x", dut.core.x0_reg, dut.core.x1_reg);
- $display("x2_reg = %08x, x3_reg = %08x", dut.core.x2_reg, dut.core.x3_reg);
- $display("x4_reg = %08x, x5_reg = %08x", dut.core.x4_reg, dut.core.x5_reg);
- $display("x6_reg = %08x, x7_reg = %08x", dut.core.x6_reg, dut.core.x7_reg);
- $display("x8_reg = %08x, x9_reg = %08x", dut.core.x8_reg, dut.core.x9_reg);
- $display("x10_reg = %08x, x11_reg = %08x", dut.core.x10_reg, dut.core.x11_reg);
- $display("x12_reg = %08x, x13_reg = %08x", dut.core.x12_reg, dut.core.x13_reg);
- $display("x14_reg = %08x, x15_reg = %08x", dut.core.x14_reg, dut.core.x15_reg);
+ $display("Round state:");
+ $display("state0_reg = 0x%08x, state1_reg = 0x%08x, state2_reg = 0x%08x, state3_reg = 0x%08x",
+ dut.core.state_reg[00], dut.core.state_reg[01], dut.core.state_reg[02], dut.core.state_reg[03]);
+ $display("state4_reg = 0x%08x, state5_reg = 0x%08x, state6_reg = 0x%08x, state7_reg = 0x%08x",
+ dut.core.state_reg[04], dut.core.state_reg[05], dut.core.state_reg[06], dut.core.state_reg[07]);
+ $display("state8_reg = 0x%08x, state9_reg = 0x%08x, state10_reg = 0x%08x, state11_reg = 0x%08x",
+ dut.core.state_reg[08], dut.core.state_reg[09], dut.core.state_reg[10], dut.core.state_reg[11]);
+ $display("state12_reg = 0x%08x, state13_reg = 0x%08x, state14_reg = 0x%08x, state15_reg = 0x%08x",
+ dut.core.state_reg[12], dut.core.state_reg[13], dut.core.state_reg[14], dut.core.state_reg[15]);
$display("");
- $display("rounds_reg = %01x", dut.core.rounds_reg);
+ $display("rounds = %01x", dut.core.rounds);
$display("qr_ctr_reg = %01x, dr_ctr_reg = %01x", dut.core.qr_ctr_reg, dut.core.dr_ctr_reg);
$display("block0_ctr_reg = %08x, block1_ctr_reg = %08x", dut.core.block0_ctr_reg, dut.core.block1_ctr_reg);
@@ -379,7 +391,7 @@ module tb_chacha();
$display("chacha_ctrl_reg = %02x", dut.core.chacha_ctrl_reg);
$display("");
- $display("data_in_reg = %064x", dut.core.data_in_reg);
+ $display("data_in = %064x", dut.core.data_in);
$display("data_out_valid_reg = %01x", dut.core.data_out_valid_reg);
$display("");
@@ -395,7 +407,7 @@ module tb_chacha();
//
// Display the accumulated test results.
//----------------------------------------------------------------
- task display_test_result();
+ task display_test_result;
begin
if (error_ctr == 0)
begin
@@ -410,28 +422,6 @@ module tb_chacha();
//----------------------------------------------------------------
- // init_dut()
- //
- // Set the input to the DUT to defined values.
- //----------------------------------------------------------------
- task init_dut();
- begin
- // Set clock, reset and DUT input signals to
- // defined values at simulation start.
- cycle_ctr = 0;
- error_ctr = 0;
- tc_ctr = 0;
- tb_clk = 0;
- tb_reset_n = 0;
- tb_cs = 0;
- tb_write_read = 0;
- tb_address = 8'h00;
- tb_data_in = 32'h00000000;
- end
- endtask // init_dut
-
-
- //----------------------------------------------------------------
// read_write_test()
//
// Simple test case that tries to read and write to the
@@ -439,7 +429,7 @@ module tb_chacha();
//
// Note: Currently not self testing. No expected values.
//----------------------------------------------------------------
- task read_write_test();
+ task read_write_test;
begin
tc_ctr = tc_ctr + 1;
@@ -484,8 +474,8 @@ module tb_chacha();
write_reg(ADDR_KEY7, key[31 : 0]);
write_reg(ADDR_IV0, iv[63 : 32]);
write_reg(ADDR_IV1, iv[31 : 0]);
- write_reg(ADDR_KEYLEN, {{31'b0000000000000000000000000000000}, key_length});
- write_reg(ADDR_ROUNDS, {{27'b000000000000000000000000000}, rounds});
+ write_reg(ADDR_KEYLEN, {{31'h0}, key_length});
+ write_reg(ADDR_ROUNDS, {{27'h0}, rounds});
end
endtask // write_parameters
@@ -499,10 +489,10 @@ module tb_chacha();
// Note: It is the callers responsibility to call the function
// when the dut is ready to react on the init signal.
//----------------------------------------------------------------
- task start_init_block();
+ task start_init_block;
begin
write_reg(ADDR_CTRL, 32'h00000001);
- #(4 * CLK_HALF_PERIOD);
+ #(2 * CLK_PERIOD);
write_reg(ADDR_CTRL, 32'h00000000);
end
endtask // start_init_block
@@ -517,17 +507,17 @@ module tb_chacha();
// Note: It is the callers responsibility to call the function
// when the dut is ready to react on the next signal.
//----------------------------------------------------------------
- task start_next_block();
+ task start_next_block;
begin
write_reg(ADDR_CTRL, 32'h00000002);
- #(4 * CLK_HALF_PERIOD);
+ #(2 * CLK_PERIOD);
write_reg(ADDR_CTRL, 32'h00000000);
if (DEBUG)
begin
$display("Debug of next state.");
dump_core_state();
- #(4 * CLK_HALF_PERIOD);
+ #(2 * CLK_PERIOD);
dump_core_state();
end
end
@@ -543,7 +533,7 @@ module tb_chacha();
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
- task wait_ready();
+ task wait_ready;
begin
while (!tb_data_out[STATUS_READY_BIT])
begin
@@ -559,7 +549,7 @@ module tb_chacha();
// Extracts all 16 data out words and combine them into the
// global extracted_data.
//----------------------------------------------------------------
- task extract_data();
+ task extract_data;
begin
read_reg(ADDR_DATA_OUT0);
extracted_data[511 : 480] = tb_data_out;
@@ -598,6 +588,34 @@ module tb_chacha();
//----------------------------------------------------------------
+ // check_name_version()
+ //
+ // Read the name and version from the DUT.
+ //----------------------------------------------------------------
+ task check_name_version;
+ reg [31 : 0] name0;
+ reg [31 : 0] name1;
+ reg [31 : 0] version;
+ begin
+ $display("*** Trying to read name and version from core.");
+ read_reg(ADDR_NAME0);
+ name0 = tb_data_out;
+ read_reg(ADDR_NAME1);
+ name1 = tb_data_out;
+ read_reg(ADDR_VERSION);
+ version = tb_data_out;
+
+ $display("DUT name: %c%c%c%c%c%c%c%c",
+ name0[31 : 24], name0[23 : 16], name0[15 : 8], name0[7 : 0],
+ name1[31 : 24], name1[23 : 16], name1[15 : 8], name1[7 : 0]);
+ $display("DUT version: %c%c%c%c",
+ version[31 : 24], version[23 : 16], version[15 : 8], version[7 : 0]);
+ $display("");
+ end
+ endtask // check_name_version
+
+
+ //----------------------------------------------------------------
// run_two_blocks_test_vector()
//
// Runs a test case with two blocks based on the given
@@ -616,7 +634,6 @@ module tb_chacha();
$display("***TC%2d-%2d started", major, minor);
$display("***-----------------");
write_parameters(key, key_length, iv, rounds);
-
start_init_block();
wait_ready();
extract_data();
@@ -690,7 +707,10 @@ module tb_chacha();
write_parameters(key, key_length, iv, rounds);
start_init_block();
+ $display("*** Started.");
wait_ready();
+ $display("*** Ready seen.");
+ dump_top_state();
extract_data();
if (extracted_data != expected)
@@ -720,18 +740,20 @@ module tb_chacha();
initial
begin : chacha_test
$display(" -- Testbench for chacha started --");
- init_dut();
- set_display_prefs(0, 0);
+ init_sim();
reset_dut();
$display("State at init after reset:");
dump_top_state();
+ // Check name and version.
+ check_name_version();
+
$display("TC1-1: All zero inputs. 128 bit key, 8 rounds.");
run_test_vector(TC1, ONE,
- 256'h0000000000000000000000000000000000000000000000000000000000000000,
+ 256'h0,
KEY_128_BITS,
- 64'h0000000000000000,
+ 64'h0,
EIGHT_ROUNDS,
512'he28a5fa4a67f8c5defed3e6fb7303486aa8427d31419a729572d777953491120b64ab8e72b8deb85cd6aea7cb6089a101824beeb08814a428aab1fa2c816081b);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 06:47:10 +0000