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diff --git a/LICENSE.txt b/LICENSE.txt
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+Copyright (c) 2011, NORDUnet A/S All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are
+met:
+- Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+
+- Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in the
+  documentation and/or other materials provided with the distribution.
+
+- Neither the name of the NORDUnet nor the names of its contributors may
+  be used to endorse or promote products derived from this software
+  without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
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+chacha
+========
+
+Verilog 2001 implementation of the ChaCha stream cipher.
+
+## Functionality ##
+This core implements ChaCha with support for 128 and 256 bit keys. The
+number of rounds can be set from two to 32 rounds in steps of two. The
+default number of rounds is eight.
+
+The core contains an internal 64-bit block counter that is automatically
+updated for each data block.
+
+
+## Performance ##
+Each quarterround takes one cycle which means that the mininum latency
+will be 4*rounds. When the core is functionally correct we will add two
+more version with 2 and 4 parallel quarterrounds respectively. The four
+quarterounds version will achieve 1 cycle/round.
+
+
+## Implementation ##
+Implementation results using the Altera Quartus 13 design tool.
+
+### Cyclone IV GX ###
+- 6233 LEs
+- 3677 registers
+- 56.1 MHz
+- 11 cycles latency
+- 2.6 Gbps performance.
+
+
+### Cyclone V GX ###
+- 2631 ALMs for logic
+- 3677 registers
+- 54.3 MHz
+- 11 cycles latency
+- 2.5 Gbps performance.
+
+
+## Status ##
+
+(2014-09-03)
+- Added a new port in the core to allow setting of the initial value of
+the counter. The top level wrapper currently sets this value to a
+constant zero.
+
+- Added the ChaCha core to Cryptech.
+