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| -rwxr-xr-x | toolruns/Makefile | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile new file mode 100755 index 0000000..6f94769 --- /dev/null +++ b/toolruns/Makefile @@ -0,0 +1,84 @@ +#=================================================================== +# +# Makefile +# -------- +# Makefile for building core and top simulation. +# +# +# Author: Joachim Strombergson +# Copyright (c) 2011, NORDUnet A/S All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of the NORDUnet nor the names of its contributors may +# be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#=================================================================== + +CORE_SRC=../src/rtl/chacha_core.v ../src/rtl/chacha_qr.v +CORE_TB_SRC=../src/tb/tb_chacha_core.v + +TOP_SRC=../src/rtl/chacha.v $(CORE_SRC) +TOP_TB_SRC=../src/tb/tb_chacha.v + +CC=iverilog + + +all: top core + + +top: $(TOP_TB_SRC) $(TOP_SRC) + $(CC) -o top.sim $(TOP_TB_SRC) $(TOP_SRC) + + +core: $(CORE_TB_SRC) $(CORE_SRC) + $(CC) -o core.sim $(CORE_SRC) $(CORE_TB_SRC) + + +sim-core: core.sim + ./core.sim + + +sim-top: top.sim + ./top.sim + + +help: + @echo "Supported targets:" + @echo "------------------" + @echo "all: Build all simulation targets." + @echo "top: Build the top simulation target." + @echo "core: Build the top simulation target." + @echo "sim-top: Run top level simulation." + @echo "sim-core: Run core level simulation." + @echo "debug: Print the internal varibles." + +clean: + rm -f core.sim + rm -f top.sim + +#=================================================================== +# EOF Makefile +#=================================================================== + |