Fixes to nits found using the verilator linter.

3 files changed, 6 insertions, 18 deletions

diff --git a/src/rtl/chacha.v b/src/rtl/chacha.v
index 8fd58f4..72792aa 100644
--- a/src/rtl/chacha.v
+++ b/src/rtl/chacha.v
@@ -191,37 +191,21 @@ module chacha(
   reg          data_in15_we;
 
   reg [31 : 0] data_out0_reg;
-  reg [31 : 0] data_out0_new;
   reg [31 : 0] data_out1_reg;
-  reg [31 : 0] data_out1_new;
   reg [31 : 0] data_out2_reg;
-  reg [31 : 0] data_out2_new;
   reg [31 : 0] data_out3_reg;
-  reg [31 : 0] data_out3_new;
   reg [31 : 0] data_out4_reg;
-  reg [31 : 0] data_out4_new;
   reg [31 : 0] data_out5_reg;
-  reg [31 : 0] data_out5_new;
   reg [31 : 0] data_out6_reg;
-  reg [31 : 0] data_out6_new;
   reg [31 : 0] data_out7_reg;
-  reg [31 : 0] data_out7_new;
   reg [31 : 0] data_out8_reg;
-  reg [31 : 0] data_out8_new;
   reg [31 : 0] data_out9_reg;
-  reg [31 : 0] data_out9_new;
   reg [31 : 0] data_out10_reg;
-  reg [31 : 0] data_out10_new;
   reg [31 : 0] data_out11_reg;
-  reg [31 : 0] data_out11_new;
   reg [31 : 0] data_out12_reg;
-  reg [31 : 0] data_out12_new;
   reg [31 : 0] data_out13_reg;
-  reg [31 : 0] data_out13_new;
   reg [31 : 0] data_out14_reg;
-  reg [31 : 0] data_out14_new;
   reg [31 : 0] data_out15_reg;
-  reg [31 : 0] data_out15_new;
 
 
   //----------------------------------------------------------------
diff --git a/src/rtl/chacha_core.v b/src/rtl/chacha_core.v
index c46b5b1..0e1158b 100644
--- a/src/rtl/chacha_core.v
+++ b/src/rtl/chacha_core.v
@@ -1327,6 +1327,12 @@ module chacha_core(
                 chacha_ctrl_we     = 1;
               end
           end
+
+
+        default:
+          begin
+
+          end
       endcase // case (chacha_ctrl_reg)
     end // chacha_ctrl_fsm
 endmodule // chacha_core
diff --git a/src/rtl/chacha_qr.v b/src/rtl/chacha_qr.v
index 1909a1c..42e644c 100644
--- a/src/rtl/chacha_qr.v
+++ b/src/rtl/chacha_qr.v
@@ -86,8 +86,6 @@ module chacha_qr(
 
       reg [31 : 0] c0;
       reg [31 : 0] c1;
-      reg [31 : 0] c2;
-      reg [31 : 0] c3;
 
       reg [31 : 0] d0;
       reg [31 : 0] d1;