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2018-10-02Reading AES result will be zero when ready is not set.Joachim Strömbergson
2018-09-27Added missing reset of registers. This fixes CT-01-001 FPGA.Joachim Strömbergson
2018-05-26Shaved off another cycle for block processing.Joachim Strömbergson
2018-05-22Updated README with latest implementation results and status for the core.Joachim Strömbergson
2018-05-22Minor cleanup of states and register sizes.Joachim Strömbergson
2018-05-22Combined all AES round operations into a single operation for a round.Joachim Strömbergson
2018-05-22Polished the wait_ready task to use defined bit index.Joachim Strömbergson
2018-05-22Updated README with implementation results.Joachim Strömbergson
2018-05-21Updated core status and implementation details.Joachim Strömbergson
2018-05-21Increased number of inverse S-boxes to 16 and removed S-box scheduling.Joachim Strömbergson
2018-05-21Cleaned up redundant wires.Joachim Strömbergson
2018-05-21Moved the Sbox used for key expansion into the key_mem.Joachim Strömbergson
2018-05-21Removed the sbox word mux. Removed ports for sbox access in the encipher ↵Joachim Strömbergson
datapath since it now has its own sboxes.
2018-05-21Removed the sword counter since it is not needed.Joachim Strömbergson
2018-05-21Connected the new S-boxes and collapsed the SubBytes operation into one ↵Joachim Strömbergson
cycle. This provides a speedup for Encipher with 2.1x.
2018-05-21Adding 16 S-boxes to the encipher datapath.Joachim Strömbergson
2018-05-21Adding task to wait for ready to be set. This allows us to measure the ↵Joachim Strömbergson
number of cycles spent doing operations.
2018-05-21Adding inital version of AES core optimized for performance.Joachim Strömbergson