index
:
core/cipher/aes_speed
master
(Old) Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)
git repositories
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Collapse
)
Author
2018-10-02
Reading AES result will be zero when ready is not set.
Joachim Strömbergson
2018-09-27
Added missing reset of registers. This fixes CT-01-001 FPGA.
Joachim Strömbergson
2018-05-26
Shaved off another cycle for block processing.
Joachim Strömbergson
2018-05-22
Updated README with latest implementation results and status for the core.
Joachim Strömbergson
2018-05-22
Minor cleanup of states and register sizes.
Joachim Strömbergson
2018-05-22
Combined all AES round operations into a single operation for a round.
Joachim Strömbergson
2018-05-22
Polished the wait_ready task to use defined bit index.
Joachim Strömbergson
2018-05-22
Updated README with implementation results.
Joachim Strömbergson
2018-05-21
Updated core status and implementation details.
Joachim Strömbergson
2018-05-21
Increased number of inverse S-boxes to 16 and removed S-box scheduling.
Joachim Strömbergson
2018-05-21
Cleaned up redundant wires.
Joachim Strömbergson
2018-05-21
Moved the Sbox used for key expansion into the key_mem.
Joachim Strömbergson
2018-05-21
Removed the sbox word mux. Removed ports for sbox access in the encipher ↵
Joachim Strömbergson
datapath since it now has its own sboxes.
2018-05-21
Removed the sword counter since it is not needed.
Joachim Strömbergson
2018-05-21
Connected the new S-boxes and collapsed the SubBytes operation into one ↵
Joachim Strömbergson
cycle. This provides a speedup for Encipher with 2.1x.
2018-05-21
Adding 16 S-boxes to the encipher datapath.
Joachim Strömbergson
2018-05-21
Adding task to wait for ready to be set. This allows us to measure the ↵
Joachim Strömbergson
number of cycles spent doing operations.
2018-05-21
Adding inital version of AES core optimized for performance.
Joachim Strömbergson