Updated core status and implementation details.

1 files changed, 9 insertions, 11 deletions

diff --git a/README.md b/README.md
index 9504ec1..3993e6c 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,5 @@
 aes_speed
 =========
-
 Speed optimized Verilog implementation of the symmetric block cipher AES
 (Advanced Encryption Standard) as specified in the NIST document [FIPS
 197](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).
@@ -11,11 +10,11 @@ is to allow a drop-in replacement in Cryptech designs.
 
 
 ## Status ##
-Just started, not done. Does not work.
+First round of optimizations done. Core similates correctly. Has not
+yet been implemented in FPGA.
 
 
 ## Introduction ##
-
 This implementation supports 128 and 256 bit keys. The
 implementation is iterative and process one 128 block at a time. Blocks
 are processed on a word level with 4 S-boxes in the data path. The
@@ -30,19 +29,18 @@ will reduce the size to about 50%. For cipher modes such as CTR, GCM
 decryption in the AES core will never be used and thus the decipher
 block processing can be removed.
 
-This is a fairly compact implementation. Further reduction could be
-achived by just having a single S-box. Similarly the performane can be
-increased by having 8 or even 16 S-boxes which would reduce the number
-of cycles to two cycles for each round.
+The core has been equipped with 16 S-boxes for encipher and 16 Inverse
+S-boxes for decipher. This allows the core to perform the SubBytes and
+InverseSubBytes operations in the AES round functions in one cycle.
+
+The key expansion does not share S-boxes with the encipher datapath, so
+the total number of S-boxes is 20.
 
 
 ## Performance and area comparison ##
-Number of cycles for the Cryptech AES core:
+Number of cycles for the Cryptech old AES core:
 - AES-128 Encipher one block with key expansion: 57
 
 
 Number of cycles for the Cryptech AES speed core:
 - AES-128 Encipher with key expansion: 27
-
-
-Resources used by the Crypteh AES core: