| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-05-22 | Minor cleanup of states and register sizes. | Joachim Strömbergson | |
| 2018-05-22 | Combined all AES round operations into a single operation for a round. | Joachim Strömbergson | |
| 2018-05-21 | Increased number of inverse S-boxes to 16 and removed S-box scheduling. | Joachim Strömbergson | |
| 2017-12-14 | Synced the AES core rtl and testbench to github. The updates does not add or ↵ | Joachim Strömbergson | |
| modify any functionality, but silence a lot of warnings, reduce code size. | |||
| 2015-12-13 | whack copyrights | Paul Selkirk | |
| 2014-11-27 | Adding RTL source files for the AES core. | Joachim Strömbergson | |
 |
index : core/cipher/aes | |
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) | git repositories |
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