| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-10-03 | Adding restriction to the API to only allow writes to controlling registers. ↵aes_speed | Joachim Strömbergson | |
| This fixes CT-01-002 FPGA. | |||
| 2018-10-02 | Reading AES result will be zero when ready is not set. | Joachim Strömbergson | |
| 2018-05-26 | Shaved off another cycle for block processing. | Joachim Strömbergson | |
| 2018-05-21 | Adding inital version of AES core optimized for performance. | Joachim Strömbergson | |
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index : core/cipher/aes | |
| Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) | git repositories |
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