diff options
author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-05-26 13:26:20 +0200 |
---|---|---|
committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-05-26 13:26:20 +0200 |
commit | c1225cb6c9843e91f3b3dfee294fc1f9309e8212 (patch) | |
tree | e6d34e55e9efc60ebae31d4f0818b3ae64a5641a /src/rtl/aes.v | |
parent | 6a39d877e450269fb216129bad8cafb7caba8a5d (diff) |
Shaved off another cycle for block processing.
Diffstat (limited to 'src/rtl/aes.v')
-rw-r--r-- | src/rtl/aes.v | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/src/rtl/aes.v b/src/rtl/aes.v index 0d719d2..ddee8f0 100644 --- a/src/rtl/aes.v +++ b/src/rtl/aes.v @@ -107,10 +107,6 @@ module aes( reg [31 : 0] key_reg [0 : 7]; reg key_we; - reg [127 : 0] result_reg; - reg valid_reg; - reg ready_reg; - //---------------------------------------------------------------- // Wires. @@ -189,16 +185,9 @@ module aes( next_reg <= 1'b0; encdec_reg <= 1'b0; keylen_reg <= 1'b0; - - result_reg <= 128'h0; - valid_reg <= 1'b0; - ready_reg <= 1'b0; end else begin - ready_reg <= core_ready; - valid_reg <= core_valid; - result_reg <= core_result; init_reg <= init_new; next_reg <= next_new; @@ -259,7 +248,7 @@ module aes( ADDR_NAME1: tmp_read_data = CORE_NAME1; ADDR_VERSION: tmp_read_data = CORE_VERSION; ADDR_CTRL: tmp_read_data = {28'h0, keylen_reg, encdec_reg, next_reg, init_reg}; - ADDR_STATUS: tmp_read_data = {30'h0, valid_reg, ready_reg}; + ADDR_STATUS: tmp_read_data = {30'h0, core_valid, core_ready}; default: begin @@ -267,7 +256,7 @@ module aes( endcase // case (address) if ((address >= ADDR_RESULT0) && (address <= ADDR_RESULT3)) - tmp_read_data = result_reg[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; + tmp_read_data = core_result[(3 - (address - ADDR_RESULT0)) * 32 +: 32]; end end end // addr_decoder |