core/cipher/aes - Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard)

Age	Commit message (Collapse)	Author
2019-01-15	Bump the version number, because new code.	Paul Selkirk

2018-10-03	Adding restriction to the API to only allow writes to controlling registers. ↵	Joachim Strömbergson
	This fixes CT-01-002 FPGA.
2018-10-02	Reading AES result will be zero when ready is not set.	Joachim Strömbergson

2018-05-26	Shaved off another cycle for block processing.	Joachim Strömbergson

2017-12-15	Adding the error port that went missing. Sloppy.	Joachim Strömbergson

2017-12-14	Synced the AES core rtl and testbench to github. The updates does not add or ↵	Joachim Strömbergson
	modify any functionality, but silence a lot of warnings, reduce code size.
2015-12-13	whack copyrights	Paul Selkirk

2015-10-02	Fixing text error in comment.	Joachim Strömbergson

2015-07-17	fix CORE_VERSION to match what we think it should be	Paul Selkirk

2015-05-16	(1) Changed name and version to reflect that it is not only AES-128 and that ↵	Joachim Strömbergson
	the core is fairly close to done. (2) Moved counter update.
2015-05-04	(1) Changed ordet of status and config addresses to conform to what we have ↵	Joachim Strömbergson
	in other cores. (2) Changed to localparam to stop polluting namespace.
2014-11-27	Adding RTL source files for the AES core.	Joachim Strömbergson