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authorJoachim StroĢˆmbergson <joachim@secworks.se>2017-12-14 16:14:03 +0100
committerJoachim StroĢˆmbergson <joachim@secworks.se>2017-12-14 16:14:03 +0100
commit67cd02c98626fc526c9e5e1790e049177190eab8 (patch)
tree5ce9d43f4baae4060425337a1dc4b2a1513e0d6b /toolruns
parent915759285c179cf99be3c17ad401c79e4b8be054 (diff)
Adding support for linting the AES core.
Diffstat (limited to 'toolruns')
-rwxr-xr-xtoolruns/Makefile6
1 files changed, 6 insertions, 0 deletions
diff --git a/toolruns/Makefile b/toolruns/Makefile
index 105524e..835a92f 100755
--- a/toolruns/Makefile
+++ b/toolruns/Makefile
@@ -52,6 +52,7 @@ TB_ENCIPHER_SRC =../src/tb/tb_aes_encipher_block.v
TB_DECIPHER_SRC =../src/tb/tb_aes_decipher_block.v
CC=iverilog
+LINT=verilator
all: top.sim core.sim keymem.sim encipher.sim decipher.sim
@@ -96,6 +97,10 @@ sim-top: top.sim
./top.sim
+lint:
+ verilator +1364-2001ext+ --lint-only -Wall $(TOP_SRC)
+
+
clean:
rm -f decipher.sim
rm -f encipher.sim
@@ -110,6 +115,7 @@ help:
@echo "Supported targets:"
@echo "------------------"
@echo "all: Build all simulation targets."
+ @echo "lint: Lint all rtl source files."
@echo "top.sim: Build top level simulation target."
@echo "core.sim: Build core level simulation target."
@echo "keymem.sim: Build key memory simulation target."