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| author | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
|---|---|---|
| committer | Joachim StroĢmbergson <joachim@secworks.se> | 2018-09-27 15:08:19 +0200 |
| commit | 1ef4aa6654070223e91930c7e5631d8ce022490a (patch) | |
| tree | afeb4ec1491932a0f9e42b8efde28f8c85e887a8 /src/rtl/aes_core.v | |
| parent | fd40ab87a7f13dd4ce6d636edd7bf7cffc265aa3 (diff) | |
Added missing reset of registers. This fixes CT-01-001 FPGA.
Diffstat (limited to 'src/rtl/aes_core.v')
0 files changed, 0 insertions, 0 deletions