Adding inital version of AES core optimized for performance.

1 files changed, 19 insertions, 24 deletions

diff --git a/README.md b/README.md
index f8a04fc..6322084 100644
--- a/README.md
+++ b/README.md
@@ -1,8 +1,17 @@
-aes
-======
+aes_speed
+=========
 
-Verilog implementation of the symmetric block cipher AES (Advanced
-Encryption Standard) as specified in the NIST document [FIPS 197](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).
+Speed optimized Verilog implementation of the symmetric block cipher AES
+(Advanced Encryption Standard) as specified in the NIST document [FIPS
+197](http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf).
+
+This core is modified version of the Cryptech AES core. Note that the
+name of the core modules are identical to that core. The purpose of this
+is to allow a drop-in replacement in Cryptech designs.
+
+
+## Status ##
+Just started, not done. Does not work.
 
 
 ## Introduction ##
@@ -27,27 +36,13 @@ increased by having 8 or even 16 S-boxes which would reduce the number
 of cycles to two cycles for each round.
 
 
-## Implementation results ##
-The core has been implemented in Altera and Xilinx FPGA devices.
-
-### Altera Cyclone IV GX ###
-- 7497 LEs
-- 2994 Regs
-- 96 MHz fmax
-- 5 cycles/round
+## Performance and area comparison ##
+Number of cycles for the Cryptech AES core:
+- TBW
 
-This means that we can do just about 2 Mblocks/s or 256 Mbps
-performance.
 
-Removing the decipher module yields:
-- 5497 LEs
-- 2855 Regs
-- 106 MHz fmax
-- 5 cycles/round
+Number of cycles for the Cryptech AES core:
+- TBW
 
 
-### Xilinx Spartan6LX-3 ###
-- 2576 slices
-- 3000 regs
-- 100 MHz
-- 5 cycles/round
+Resources used by the Crypteh AES core: