Clarified the cycle times that was confusing regarding key expansion. Fixed minor speling errror.HEADmaster

1 files changed, 10 insertions, 6 deletions

diff --git a/README.md b/README.md
index 0d552dd..ec99300 100644
--- a/README.md
+++ b/README.md
@@ -10,8 +10,8 @@ is to allow a drop-in replacement in Cryptech designs.
 
 
 ## Status ##
-Second round of optimizations done. Core similates correctly. Core has
-been implemented in FPGA, but not functionally tested in real HW.
+Second round of optimizations done. The core has been implemented in
+FPGA and tested in real HW.
 
 
 ## Introduction ##
@@ -36,12 +36,16 @@ the total number of S-boxes is 40.
 
 ## Performance comparison
 Number of cycles for the old Cryptech AES core:
-- AES-128 Encipher one block with key expansion: 57
-- AES-256 Decipher one block with key expansion: 77
+- AES-128 Encipher one block: 57
+- AES-256 Decipher one block: 77
 
 Number of cycles for the Cryptech AES speed core:
-- AES-128 Encipher one block with key expansion: 16
-- AES-255 Decipher one block with key expansion: 20
+- AES-128 Encipher one block: 16
+- AES-255 Decipher one block: 20
+
+Note that these latency numbers are after key expansion. The given key
+must be expanded byt asserting the init control bit and wait for ready
+to be asserted. Key expansion takes about 10 to 14 cycles.
 
 
 ## Implementation comparison