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authorJoachim StroĢˆmbergson <joachim@assured.se>2019-06-09 21:18:14 +0200
committerJoachim StroĢˆmbergson <joachim@assured.se>2019-06-09 21:18:14 +0200
commit4c03b5b0542988680821ec10b50fb93a9a0e6389 (patch)
tree0359edfb917e90b5c7375e18362824e08bfdf0ed /README.md
parenta86d49407d86cde1e782b7e54fc6848f450cba23 (diff)
Clarified the cycle times that was confusing regarding key expansion. Fixed minor speling errror.HEADmaster
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@@ -10,8 +10,8 @@ is to allow a drop-in replacement in Cryptech designs.
## Status ##
-Second round of optimizations done. Core similates correctly. Core has
-been implemented in FPGA, but not functionally tested in real HW.
+Second round of optimizations done. The core has been implemented in
+FPGA and tested in real HW.
## Introduction ##
@@ -36,12 +36,16 @@ the total number of S-boxes is 40.
## Performance comparison
Number of cycles for the old Cryptech AES core:
-- AES-128 Encipher one block with key expansion: 57
-- AES-256 Decipher one block with key expansion: 77
+- AES-128 Encipher one block: 57
+- AES-256 Decipher one block: 77
Number of cycles for the Cryptech AES speed core:
-- AES-128 Encipher one block with key expansion: 16
-- AES-255 Decipher one block with key expansion: 20
+- AES-128 Encipher one block: 16
+- AES-255 Decipher one block: 20
+
+Note that these latency numbers are after key expansion. The given key
+must be expanded byt asserting the init control bit and wait for ready
+to be asserted. Key expansion takes about 10 to 14 cycles.
## Implementation comparison