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<h1>toggle</h1>

<h2>Introduction</h2>

<p>This repo contains a simple deign that toggles an ouput pin. The toggle
is in sync with the given sys_clk, but the toggle circuit divides down
the clock. The divisor is build time defined.</p>

<p>The design is used in the Cryptech FPGA design to observe internal
clock frequencies.</p>

<h2>Status</h2>

<p>Has been simulated with Icarus Verilog.</p>

[[RepositoryIndex(format=table,glob=user/js/toggle)]]

Clone https://git.cryptech.is/user/js/toggle.git