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diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexp b/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexp new file mode 100644 index 0000000..a53e484 --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fmath%2Fmodexp @@ -0,0 +1,108 @@ +{{{ +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +}}} + +{{{ +#!html +<h1>modexp</h1> + +<p>Modular exponentiation core for implementing public key algorithms such +as RSA, DH, ElGamal etc.</p> + +<p>The core calculates the following function:</p> + +<p>C = M ** e mod N</p> + +<p>M is a message with a length of n bits + e is the exponent with a length of m bits + N is the modulus with a length of n bits</p> + +<p>The size n be one and up to and including 8192 bits in steps of 32 +bits.</p> + +<p>The size m be one and up to and including 8192 bits in steps of 32 +bits.</p> + +<p>The core has a 32-bit memory like interface, but provides status signals +to inform the system that a given operation has is done. Additionally, +any errors will also be asserted.</p> + +<p>The core is written in Verilog 2001 and suitable for implementation in +FPGA and ASIC devices. No vendor specific macros are used in the code.</p> + +<h2>Implementation details</h2> + +<p>The core is iterative with 32-bit operands and not the fastest core on +the planet.</p> + +<h2>Future developments</h2> + +<ul> +<li><p>The core will perform blinding to protect against side channel +attacks.</p></li> +<li><p>Increased operands to 64-, 128-, or possibly even 256 bits for +increased performance.</p></li> +</ul> + +<h2>FPGA-results</h2> + +<h2>Altera Cyclone-V</h2> + +<ul> +<li>203 registers</li> +<li>387 ALMs</li> +<li>106496 block memory bits</li> +<li>107 MHz</li> +</ul> + +<h3>Xilinx Artix-7 100T</h3> + +<ul> +<li>160 registers</li> +<li>565 LUTs</li> +<li>13 RAMB18E1 block memories</li> +<li>160 MHz</li> +</ul> + +<h3>Xilinx Spartan-6 LX45</h3> + +<ul> +<li>169 registers</li> +<li>589 LUTs</li> +<li>13 RAMB8BWER block memories</li> +<li>136 MHz</li> +</ul> + +<h2>Status</h2> + +<p><strong><em>(2015-04-27)</em></strong></p> + +<p>Modexp simulation with exponent and modolus with up to 1280 bits +simulates. The auto test generation system works. Implementation in +different FPGA types and vendors works.</p> + +<p><strong><em>(2015-04-23)</em></strong></p> + +<p>The Montgomery multiplication module works. The Residue calculation +module works. Top level integration and debugging is onging. The core +does not yet work and there are dragons to be found.</p> + +<p><strong><em>(2014-12-07)</em></strong></p> + +<p>Renamed the core tom modexp from rsa to make it more clear that it +provides generic modular exponentiation, not RSA.</p> + +<p><strong><em>(2014-10-01)</em></strong></p> + +<p>Very early phase. Started to collect information and drawing some rough +ideas on paper.</p> +}}} + +[[RepositoryIndex(format=table,glob=core/math/modexp)]] + +|| Clone `https://git.cryptech.is/core/math/modexp.git` || |