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diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md new file mode 100644 index 0000000..7a2532d --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fcomm%2Fuart.md @@ -0,0 +1,27 @@ +``` +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +``` + +``` +#!html +<h1>uart</h1> + +<p>A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.</p> + +<p>This UART used to be in coretest, but has been moved out as a separate +project.</p> + +<p>The current implementation supports the ability to set the bit rate as +well as number of data- and stop bits by writing to control addresses +via the control interface.</p> +``` + +[[RepositoryIndex(format=table,glob=core/comm/uart)]] + +| Clone `https://git.cryptech.is/core/comm/uart.git` | +|---| |