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@@ -24,17 +24,13 @@ source out of the can. for v.2 (or whatever) we would move it down to the FPGA
Verilog.
## FPGA Overview
-![HW_sketch_v0001.png]({attach}RoughV1/HW_sketch_v0001.png)
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+![HW_sketch_v0001.png]({attach}/RoughV1/HW_sketch_v0001.png)
+<br/>
+<br/>
## Sketch of TRNG Chain
-![HW_RNG.png]({attach}RoughV1/HW_RNG.png)
-
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+![HW_RNG.png]({attach}/RoughV1/HW_RNG.png)
+<br/>
+<br/>
## Off-FPGA