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Diffstat (limited to 'pelican/content/InterconnectStandards.md')
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1 files changed, 34 insertions, 34 deletions
diff --git a/pelican/content/InterconnectStandards.md b/pelican/content/InterconnectStandards.md index ee13711..11a547c 100644 --- a/pelican/content/InterconnectStandards.md +++ b/pelican/content/InterconnectStandards.md @@ -54,10 +54,10 @@ There are also non-technical differences: ## Description of Standards ### AMBA -AMBA (Advanced Microcontroller Bus Architecture) [#fn1 (1)], [#fn2 (2)] is a family of +AMBA (Advanced Microcontroller Bus Architecture) [(1)](#fn1), [(2)](#fn2) is a family of interconnect standards from ARM Ltd. AMBA is widely used in systems implemented in ASICs (for example mobile phone platforms), but are also -used in FPGAs. AMBA is for example used by the LEON [#fn3 (3)] processor +used in FPGAs. AMBA is for example used by the LEON [(3)](#fn3) processor cores and subsystem GRLIB. AMBA currently contains four main interconnect types: @@ -90,9 +90,9 @@ things like tracing etc.) The license model for AMBA is _Open_ according to ARM. This seems to mean that one can use AMBA to build a system. But at the same time, ARM has intellectual properties to parts of the technology as well as -trademarks. For more information on ARM licensing, see [#fn4 (4)]. +trademarks. For more information on ARM licensing, see [(4)](#fn4). -The OpenCores project [#fn7 (7)] lists several cores as well as tools for +The OpenCores project [(7)](#fn7) lists several cores as well as tools for different AMBA interconnect types. Pros: @@ -123,9 +123,9 @@ Cons: ### Avalon -Avalon [#fn5 (5)] is a proprietary switch fabric interconnect from Altera +Avalon [(5)](#fn5) is a proprietary switch fabric interconnect from Altera corporation. It is used in systems developed using the Altera Nios-II -[#fn6 (6)] family of soft processor cores and related peripherals. +[(6)](#fn6) family of soft processor cores and related peripherals. According to Altera, the license for Avalon is open: "Avalon interfaces are an open standard. No license or royalty is required to develop and @@ -133,7 +133,7 @@ sell products that use, or are based on Avalon interfaces." As far as we can discern, Avalon is not generally used outside of Altera based designs and not supported by a large group of third party -vendors. The OpenCores project lists only a few cores that uses Avalon +vendors. The [OpenCores](OpenCores.md) project lists only a few cores that uses Avalon as interface standard. = @@ -159,15 +159,15 @@ Cons: ### CoreConnect -CoreConnect [#fn8 (8)] is an interconnect standard initially developed by +CoreConnect [(8)](#fn8) is an interconnect standard initially developed by IBM. The standard is now used by several vendors, for example the -FPGA-vendor Xilinx[#fn9 (9)]. +FPGA-vendor Xilinx[(9)](#fn9). Similarly to AMBA, CoreConnect contains several types of buses providing simple peripheral access (DCR), high speed access for processor based systems (OPB), as well as multicore solutions (PLB). -The license for CoreConnect is granted by IBM [#fn10 (10)]. The license seems to be +The license for CoreConnect is granted by IBM [(10)](#fn10). The license seems to be an AS IS-license, but contains a lot of other regulations. IBM holds a number of patents related to CoreConnect (see the license agreement). @@ -184,9 +184,9 @@ Cons: ### OCP -The Open Core Protocol [#fn11 (11)] is a vendor neutral open interconnect standard -being developed by the EDA standards organisation Accellera [#fn12 (12)]. The -standards was previously developed by the vendor organisation OCP-IP [#fn13 (13)], +The Open Core Protocol [(11)](#fn11) is a vendor neutral open interconnect standard +being developed by the EDA standards organisation Accellera [(12)](#fn12). The +standards was previously developed by the vendor organisation OCP-IP [(13)](#fn13), but were transferred to Accellera in October 2013. Like AMBA, OCP contains a wide range of interconnect types from simple @@ -198,7 +198,7 @@ very few open cores using OCP. OpenCores only lists a few cores and they are all bridges used to connect OCP to AMBA or Wishbone. The license for accessing the specification itself is an amended AS -IS-type license[#fn14 (14)]. The license for the interconnect seems to be rather +IS-type license[(14)](#fn14). The license for the interconnect seems to be rather open. Pros: @@ -213,7 +213,7 @@ Cons: ### Wishbone -Wishbone [#fn15 (15)][#fn16 (16)] (often written WISHBONE) is an open interconnect +Wishbone [(15)](#fn15)[(16)](#fn16) (often written WISHBONE) is an open interconnect standard developed by members of the OpenCore project as an alternative to commercial solutions - primarily AMBA. @@ -228,7 +228,7 @@ well as creating a Wishbone connected system with different types of interconnect solutions. The main use is related to the OpenRISC CPU core platform -[#fn17 (17)][#fn18 (18)]. OpenCores lists a huge selection of cores with Wishbone +[(17)](#fn17)[(18)](#fn18). OpenCores lists a huge selection of cores with Wishbone support. The majority of these cores have LGPL and GPL licenses. There are also third party commercial vendors that support Wishbone cores and systems. @@ -274,41 +274,41 @@ and thus reduce the interest Cryptech as a HSM solution. ## References -[=#fn1 (1)] https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture +[(1)](=#fn1) https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture -[=#fn2 (2)] http://www.arm.com/products/system-ip/amba/amba-open-specifications.php +[(2)](=#fn2) http://www.arm.com/products/system-ip/amba/amba-open-specifications.php -[=#fn3 (3)] https://en.wikipedia.org/wiki/LEON +[(3)](=#fn3) https://en.wikipedia.org/wiki/LEON -[=#fn4 (4)] http://www.arm.com/products/system-ip/amba/index.php?tab=AMBA+Trademark+Guidelines +[(4)](=#fn4) http://www.arm.com/products/system-ip/amba/index.php?tab=AMBA+Trademark+Guidelines -[=#fn5 (5)] http://www.altera.com/literature/manual/mnl_avalon_spec.pdf +[(5)](=#fn5) http://www.altera.com/literature/manual/mnl_avalon_spec.pdf -[=#fn6 (6)] http://www.altera.com/devices/processor/nios2/ni2-index.html +[(6)](=#fn6) http://www.altera.com/devices/processor/nios2/ni2-index.html -[=#fn7 (7)] http://opencores.org/ +[(7)](=#fn7) http://opencores.org/ -[=#fn8 (8)] https://en.wikipedia.org/wiki/CoreConnect +[(8)](=#fn8) https://en.wikipedia.org/wiki/CoreConnect -[=#fn9 (9)] http://www.xilinx.com/products/intellectual-property/dr_pcentral_coreconnect.htm +[(9)](=#fn9) http://www.xilinx.com/products/intellectual-property/dr_pcentral_coreconnect.htm -[=#fn10 (10)] http://www.xilinx.com/ipcenter/doc/ibm_click_core_connect_license.pdf +[(10)](=#fn10) http://www.xilinx.com/ipcenter/doc/ibm_click_core_connect_license.pdf -[=#fn11 (11)] https://en.wikipedia.org/wiki/Open_Core_Protocol +[(11)](=#fn11) https://en.wikipedia.org/wiki/Open_Core_Protocol -[=#fn12 (12)] https://en.wikipedia.org/wiki/Accellera +[(12)](=#fn12) https://en.wikipedia.org/wiki/Accellera -[=#fn13 (13)] http://www.ocpip.org/ +[(13)](=#fn13) http://www.ocpip.org/ -[=#fn14 (14)] http://www.ocpip.org/license_signup.php +[(14)](=#fn14) http://www.ocpip.org/license_signup.php -[=#fn15 (15)] http://opencores.org/opencores,wishbone +[(15)](=#fn15) http://opencores.org/opencores,wishbone -[=#fn16 (16)] https://en.wikipedia.org/wiki/Wishbone_(computer_bus) +[(16)](=#fn16) https://en.wikipedia.org/wiki/Wishbone_(computer_bus) -[=#fn17 (17)] http://openrisc.net/ +[(17)](=#fn17) http://openrisc.net/ -[=#fn18 (18)] http://opencores.org/or1k/Main_Page +[(18)](=#fn18) http://opencores.org/or1k/Main_Page ## Copyright and License |