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Diffstat (limited to 'pelican/content/AlphaBoardComponents.md')
| -rw-r--r-- | pelican/content/AlphaBoardComponents.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/pelican/content/AlphaBoardComponents.md b/pelican/content/AlphaBoardComponents.md index 3dfd1fa..ee9da4a 100644 --- a/pelican/content/AlphaBoardComponents.md +++ b/pelican/content/AlphaBoardComponents.md @@ -104,7 +104,7 @@ The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by -* Suggestion for FPGA config memory is ["M25P128 EEPROM from Micron"](http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb), with a jumper controlling the write-enable pin. +* Suggestion for FPGA config memory is [M25P128 EEPROM from Micron](http://www.micron.com/parts/nor-flash/serial-nor-flash/m25p128-vme6gb), with a jumper controlling the write-enable pin. * Suggested MUX is the Quad 2-channel Analog Switch: ON Semi. MC14551B [http://www.onsemi.com/pub_link/Collateral/MC14551B-D.PDF](http://www.onsemi.com/pub_link/Collateral/MC14551B-D.PDF) @@ -188,7 +188,7 @@ The main CPU is a ST Microelectronics STM32F429BIT6 Cortex-M4 based MCU running ### External RAM The STM32 CPU supports two separate SDRAM banks. We use both of them with as big SDRAM chips we can find for each bank. The chip used is 64 MByte for a total of 128 Mbyte RAM. -* ["ISSI IS45S32160F 64 MByte SDRAM with 32 bit data interface"](http://www.issi.com/WW/pdf/42-45R-S-32160F.pdf) +* [ISSI IS45S32160F 64 MByte SDRAM with 32 bit data interface](http://www.issi.com/WW/pdf/42-45R-S-32160F.pdf) |