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-{{{
-#!htmlcomment
-
-This page is maintained automatically by a script.  Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs.  Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-}}}
-
-{{{
-#!html
-<h1>aes_speed</h1>
-
-<p>Speed optimized Verilog implementation of the symmetric block cipher AES
-(Advanced Encryption Standard) as specified in the NIST document <a href="http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf">FIPS
-197</a>.</p>
-
-<p>This core is modified version of the Cryptech AES core. Note that the
-name of the core modules are identical to that core. The purpose of this
-is to allow a drop-in replacement in Cryptech designs.</p>
-
-<h2>Status</h2>
-
-<p>Second round of optimizations done. Core similates correctly. Core has
-been implemented in FPGA, but not functionally tested in real HW.</p>
-
-<h2>Introduction</h2>
-
-<p>This implementation supports 128 and 256 bit keys. The
-implementation is iterative and process one 128 block at a time.</p>
-
-<p>The encipher and decipher block processing datapaths are separated and
-basically self contained given access to a set of round keys and a
-block. This makes it possible to hard wire either encipher or decipher
-and allow the build tools to optimize away the other functionality which
-will reduce the size to about 50%. For cipher modes such as CTR, GCM
-decryption in the AES core will never be used and thus the decipher
-block processing can be removed.</p>
-
-<p>The core has been equipped with 16 S-boxes for encipher and 16 Inverse
-S-boxes for decipher. This allows the core to perform the SubBytes and
-InverseSubBytes operations in the AES round functions in one cycle.</p>
-
-<p>The key expansion does not share S-boxes with the encipher datapath, so
-the total number of S-boxes is 40.</p>
-
-<h2>Performance comparison</h2>
-
-<p>Number of cycles for the old Cryptech AES core:</p>
-
-<ul>
-<li>AES-128 Encipher one block with key expansion: 57</li>
-<li>AES-256 Decipher one block with key expansion: 77</li>
-</ul>
-
-<p>Number of cycles for the Cryptech AES speed core:</p>
-
-<ul>
-<li>AES-128 Encipher one block with key expansion: 16</li>
-<li>AES-255 Decipher one block with key expansion: 20</li>
-</ul>
-
-<h2>Implementation comparison</h2>
-
-<p>Implementation results for Xilinx Artix7-t200.</p>
-
-<p>Old Cryptech AES core:</p>
-
-<ul>
-<li>2094 slices</li>
-<li>2854 regs</li>
-<li>114 MHz (8.76ns)</li>
-</ul>
-
-<p>Cryptec AES speed core:</p>
-
-<ul>
-<li>2112 slices</li>
-<li>2984 regs</li>
-<li>116 MHz. (8.62ns)</li>
-</ul>
-}}}
-
-[[RepositoryIndex(format=table,glob=user/sra/aes_merged)]]
-
-|| Clone `https://git.cryptech.is/user/sra/aes_merged.git` ||