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authorRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
commit891730d13b324fad916572a82f0bd610c5de9aad (patch)
treef46c94ddfff34f15aafe7cac0596716d1c13c412 /raw-wiki-dump/GitRepositories%2Fuser%2Fshatov%2Fmodexpng_fpga_model
parentb092ffbcbe2c9398494f7dc9db6f0796971633e0 (diff)
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-{{{
-#!htmlcomment
-
-This page is maintained automatically by a script. Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs. Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-}}}
-
-{{{
-#!html
-<h1>modexpng_fpga_model</h1>
-
-<p>Math model of ModExpNG IP core. The model mimics how an FPGA does modular exponentiation.</p>
-
-<p>First use the scripts from the <code>vector/</code> folder to generate and format a keypair vector, then edit the <i>DUMP_*</i> switches in <code>modexpng_fpga_model.py</code> to dump the desired internal values. The <i>FORCE_OVERFLOW</i> setting artificially forces the virtually neven seen internal interim overflow situation and allows its handler to be tested. You can also un-comment the _#c.dump_banks()_ line and move it anywhere within _sign_using_crt()_ and/or _sign_without_crt()_ to dump the contents of entire core's memory.</p>
-}}}
-
-[[RepositoryIndex(format=table,glob=user/shatov/modexpng_fpga_model)]]
-
-|| Clone `https://git.cryptech.is/user/shatov/modexpng_fpga_model.git` ||