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authorRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
committerRob Austein <sra@hactrn.net>2020-09-13 23:06:24 +0000
commit891730d13b324fad916572a82f0bd610c5de9aad (patch)
treef46c94ddfff34f15aafe7cac0596716d1c13c412 /raw-wiki-dump/GitRepositories%2Fuser%2Fjs%2Ffpga_mkm
parentb092ffbcbe2c9398494f7dc9db6f0796971633e0 (diff)
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-{{{
-#!htmlcomment
-
-This page is maintained automatically by a script. Don't modify this page by hand,
-your changes will just be overwritten the next time the script runs. Talk to your
-Friendly Neighborhood Repository Maintainer if you need to change something here.
-
-}}}
-
-{{{
-#!html
-<h1>fpga-mkm</h1>
-
-<h2>Introduction</h2>
-
-<p>This core implements a FPGA based, active Master Key Memory (MKM).</p>
-
-<p>The memory provides access control, anti-remanence functionality and
-tamper detection protection with ns zeriosation latency.</p>
-
-<p>The target FPGA family is the Lattice iCE40 that can be kept in stand-by
-with a small battery. The target design flow is the
-[http://www.clifford.at/icestorm/ "Project IceStorm"] fully open source
-Verilog-to-Bitstream flow for iCE40 FPGAs.</p>
-
-<p>The core provides a SPI slave interface for connectivity and one or more
-tamper event inputs. Finally there might be a LED that provides
-status. At least during debugging.</p>
-
-<h2>Status</h2>
-
-<p>SPI slave interface to send and receive bytes has been implemented and
-somewhat verified. Command parser and response handler that talks to the
-SPI slave has been started, but not been completed.</p>
-
-<p>The memory with the tamper respons has been implemented, but not yet
-been verified.</p>
-
-<p>Toolchain etc has been setup for the ICEstick.</p>
-
-<h2>Implementation details</h2>
-
-<h2>Implementation results</h2>
-
-<p>TBW.</p>
-}}}
-
-[[RepositoryIndex(format=table,glob=user/js/fpga_mkm)]]
-
-|| Clone `https://git.cryptech.is/user/js/fpga_mkm.git` ||