diff options
author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:15:43 +0000 |
---|---|---|
committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:21:33 +0000 |
commit | 13d0f55865f8b1b851ce1e84597b144c5fd41662 (patch) | |
tree | 7b6ff6916f6596f64ec0d2657ae040abd5e18ed9 /raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md | |
parent | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (diff) |
GC
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md')
-rw-r--r-- | raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md b/raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md deleted file mode 100644 index 02b3a16..0000000 --- a/raw-wiki-dump/GitRepositories%2Ftest%2Fcoretest_fpga_entropy.md +++ /dev/null @@ -1,50 +0,0 @@ -``` -#!htmlcomment - -This page is maintained automatically by a script. Don't modify this page by hand, -your changes will just be overwritten the next time the script runs. Talk to your -Friendly Neighborhood Repository Maintainer if you need to change something here. - -``` - -``` -#!html -<h1>coretest_fpga_entropy</h1> - -<p>Coretest system for testing FPGA based entropy source.</p> - -<h2>Introduction</h2> - -<p>This project is a coretest system dedicated to test entropy sources -within a FPGA device. The specific entropy source is based on a digital -oscillator design by Bernd Paysan. In this entropy source, we use six -instances with different frequencies. The oscillator outputs are -combined to generate a bit value. 32 bit values are combined to create a -random word.</p> - -<p>The system uses the coretest module to read and write 32-bit data to -core, In this case it allows a caller to read generated random 16-bit -values from the entropy source. The 16 bit data is in the LSB of the -word.</p> - -<p>The completc system contains a UART core for external access. The -project contains pin assignments etc to implement the system on a -TerasIC C5G board.</p> - -<h2>Implementation details.</h2> - -<p>This FPGA system consists of the following components:</p> - -<ul> -<li>The FPGA entropy source core</li> -<li>The UART core</li> -<li>The coretest core</li> -</ul> - -<p>There are pin assignments and clock defines for the TerasIC C5G board.</p> -``` - -[[RepositoryIndex(format=table,glob=test/coretest_fpga_entropy)]] - -| Clone `https://git.cryptech.is/test/coretest_fpga_entropy.git` | -|---| |