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author | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2020-09-13 23:10:21 +0000 |
commit | 3aa8b1dd6e0f504ef83da99f8c9cdb2532f948f5 (patch) | |
tree | ca300cbdbc9b1ca3224441e50375d94c092223e8 /raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md | |
parent | 4ba5e00d5cdd42087a76e379cc39604b2da89ea4 (diff) |
Initial conversion pass
Diffstat (limited to 'raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md')
-rw-r--r-- | raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md b/raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md new file mode 100644 index 0000000..f7b2a72 --- /dev/null +++ b/raw-wiki-dump/GitRepositories%2Fcore%2Fplatform%2Fterasic_c5g.md @@ -0,0 +1,40 @@ +``` +#!htmlcomment + +This page is maintained automatically by a script. Don't modify this page by hand, +your changes will just be overwritten the next time the script runs. Talk to your +Friendly Neighborhood Repository Maintainer if you need to change something here. + +``` + +``` +#!html +<h1>platform/terasic_c5g</h1> + +<p>Platform-specific files for the TerasIC C5G development board.</p> + +<h2>Introduction</h2> + +<p>This includes the Verilog top-level files and build systems for Terasic +with a UART interface.</p> + +<h2>Status</h2> + +<p><strong><em>(2015-03-16)</em></strong> +Reorganized. Built using Altera Quarus 14.1.</p> + +<p><strong><em>(2014-03-07)</em></strong> +Initial version. Build using Altera Quarus 13.1.</p> + +<ul> +<li>Cyclone 5 GX device</li> +<li>2847 ALMs and</li> +<li>3665 registers</li> +<li>86 MHz</li> +</ul> +``` + +[[RepositoryIndex(format=table,glob=core/platform/terasic_c5g)]] + +| Clone `https://git.cryptech.is/core/platform/terasic_c5g.git` | +|---| |