Whack with club until all links pass linkchecker

Most of these weren't really links at all, just unquoted CamelCase.

18 files changed, 51 insertions, 51 deletions

diff --git a/pelican/content/ASICImplementations.md b/pelican/content/ASICImplementations.md
index f3ce441..ba997c7 100644
--- a/pelican/content/ASICImplementations.md
+++ b/pelican/content/ASICImplementations.md
@@ -23,7 +23,7 @@ features from IEEE 1364-2001 (aka Verilog 2001).
 
 All RTL code is divided into modules that contain one process for register updates and reset (*reg_update*), one or more combinational processes for datapath and support logic such as counters. Finally if needed, each module has a separate process that implements the logic for the final state machine that controls the behaviour of the module.
 
-All cores are divided into a core, for example *sha256_core.v* and a number of submodules the core instantiates. The core provides raw, wide ports (256 bit wide key for AES for example) that is not suitable to use in a stand alone system. Instead each core comes with a top level wrapper, for example *sha256.v*. This top level wrapper contains all registers and logic needed to provide all functionality of the core via a simple 32-bit memory like interface. If the core is going to be used as a tightly integrated submodule, the wrapper can be discarded. Similarly, if the core is going to be used in a bus system that use a specific bus standard such as AMBA AHB, [CoreConnect]({filename}CoreConnect.md) or WISHBONE, only the top level wrapper will be needed to be replaced or modified to match the desired bus standard.
+All cores are divided into a core, for example *sha256_core.v* and a number of submodules the core instantiates. The core provides raw, wide ports (256 bit wide key for AES for example) that is not suitable to use in a stand alone system. Instead each core comes with a top level wrapper, for example *sha256.v*. This top level wrapper contains all registers and logic needed to provide all functionality of the core via a simple 32-bit memory like interface. If the core is going to be used as a tightly integrated submodule, the wrapper can be discarded. Similarly, if the core is going to be used in a bus system that use a specific bus standard such as AMBA AHB, CoreConnect or WISHBONE, only the top level wrapper will be needed to be replaced or modified to match the desired bus standard.
 
 The RTL code does not explicitly instantiate any hard macros such as
 memories, multipliers, etc.  Instead all such functions are left to the
diff --git a/pelican/content/BerlinWorkshop.md b/pelican/content/BerlinWorkshop.md
index 09227a2..eac683c 100644
--- a/pelican/content/BerlinWorkshop.md
+++ b/pelican/content/BerlinWorkshop.md
@@ -30,7 +30,7 @@ Alpha Board cost: if you are an alpha tester and plan to take an alpha board hom
 | 1100 | Break
 | 1130 | Hands-on testing
 |      | - get binary packages running on participants' own laptops ([BinaryPackages]({filename}BinaryPackages.md))
-|      | - [OpenDNSSEC](OpenDNSSEC) is a guide for how to initialize a rev03 board and use it to sign a zone using OpenDNNSSEC - use as a baseline for own testing and experimentation with PKCS11-based applications.
+|      | - [OpenDNSSEC]({filename}OpenDNSSEC.md) is a guide for how to initialize a rev03 board and use it to sign a zone using OpenDNNSSEC - use as a baseline for own testing and experimentation with PKCS11-based applications.
 | 1230 | Buffet lunch
 | 1330 | Hands-on testing continues
 | 1500 | Coffee break
diff --git a/pelican/content/CoretestHashesNovena.md b/pelican/content/CoretestHashesNovena.md
index 9e846a9..2c427b9 100644
--- a/pelican/content/CoretestHashesNovena.md
+++ b/pelican/content/CoretestHashesNovena.md
@@ -217,7 +217,7 @@ The expected build time should be something like 5 and 10 minutes, depending on
 Some measured build times for the design:
 
 
-- 5,30 minutes on [MacbookPro]({filename}MacbookPro.md) 2013 with tools in 64-bit SUSE Linux in VM
+- 5,30 minutes on MacbookPro 2013 with tools in 64-bit SUSE Linux in VM
 - 9,20 minutes on AMD A10-6800K with tools in Windows 7 in Virtualbox VM with one CPU core and 4 GByte RAM.
 
 
diff --git a/pelican/content/DNSSEC.md b/pelican/content/DNSSEC.md
index 419a419..427402b 100644
--- a/pelican/content/DNSSEC.md
+++ b/pelican/content/DNSSEC.md
@@ -5,4 +5,4 @@ Date: 2016-12-15 22:43
 # DNSSEC
 
 
-- [DNSSEC Requirements]({filename}DNSSEC/Requirements.md)
+- [DNSSEC Requirements]({filename}DNSSEC-Requirements.md)
diff --git a/pelican/content/DevelopersGuide.md b/pelican/content/DevelopersGuide.md
index 79e718e..215d69c 100644
--- a/pelican/content/DevelopersGuide.md
+++ b/pelican/content/DevelopersGuide.md
@@ -19,7 +19,7 @@ Date: 2016-12-15 22:39
 
 
 
-* EDAToolchainSurvey"
+* EDAToolchainSurvey
 
 
 ## Building the Bitstream
diff --git a/pelican/content/DocMeet.md b/pelican/content/DocMeet.md
index d76150f..b253c8d 100644
--- a/pelican/content/DocMeet.md
+++ b/pelican/content/DocMeet.md
@@ -13,4 +13,4 @@ Date: 2016-12-15 22:39
 ## Documents
 
 * [140109.cryptech.pdf Presentation - Overview of Project with Funding Requests]({attach}/DocMeet/140109.cryptech.pdf)
-* [[attachment:141002.cryptech-iij.pdf|141002.cryptech-iij.pdf [CrypTech]({filename}CrypTech.md) Presentation at Open IIJ Seminar]]
+* [[attachment:141002.cryptech-iij.pdf|141002.cryptech-iij.pdf CrypTech Presentation at Open IIJ Seminar]]
diff --git a/pelican/content/GettingStartedNovena.md b/pelican/content/GettingStartedNovena.md
index 135a62e..68b55ed 100644
--- a/pelican/content/GettingStartedNovena.md
+++ b/pelican/content/GettingStartedNovena.md
@@ -141,7 +141,7 @@ The PKCS11 token is in /usr/lib/libpkcs11.so. In order to start using it you nee
 (echo 12345678;echo 1234) | sudo p11util --set-so-pin --set-user-pin --pin-from-stdin
 ```
 
-It is strongly suggested to change the so pin and pin (in that order above) to something sensible. Now your token is ready to use. Your favorite PKCS11-client may or may not work depending on the state of support for PKCS11 function calls - please open tickets for whatever is missing. If you want/need to talk PKCS11 from another host, you could install and configure [PKCS11Proxy](PKCS11Proxy) on both the novena and your host. Note that currently pkcs11-proxy doesn't handle differing word-lengths so your client-side will have to be 32bit (since the novena is).
+It is strongly suggested to change the so pin and pin (in that order above) to something sensible. Now your token is ready to use. Your favorite PKCS11-client may or may not work depending on the state of support for PKCS11 function calls - please open tickets for whatever is missing. If you want/need to talk PKCS11 from another host, you could install and configure [PKCS11Proxy]({filename}PKCS11Proxy.md) on both the novena and your host. Note that currently pkcs11-proxy doesn't handle differing word-lengths so your client-side will have to be 32bit (since the novena is).
 
 
 ## Setting up the lab signer
diff --git a/pelican/content/InterconnectStandards.md b/pelican/content/InterconnectStandards.md
index 3896a83..a31da2c 100644
--- a/pelican/content/InterconnectStandards.md
+++ b/pelican/content/InterconnectStandards.md
@@ -133,7 +133,7 @@ sell products that use, or are based on Avalon interfaces."
 
 As far as we can discern, Avalon is not generally used outside of Altera
 based designs and not supported by a large group of third party
-vendors. The [OpenCores]({filename}OpenCores.md) project lists only a few cores that uses Avalon
+vendors. The OpenCores project lists only a few cores that uses Avalon
 as interface standard.
 
 =
@@ -274,41 +274,41 @@ and thus reduce the interest Cryptech as a HSM solution.
 
 
 ## References
-[(1)](=#fn1) https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture
+1. https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture
 
-[(2)](=#fn2) http://www.arm.com/products/system-ip/amba/amba-open-specifications.php
+2. http://www.arm.com/products/system-ip/amba/amba-open-specifications.php
 
-[(3)](=#fn3) https://en.wikipedia.org/wiki/LEON
+3. https://en.wikipedia.org/wiki/LEON
 
-[(4)](=#fn4) http://www.arm.com/products/system-ip/amba/index.php?tab=AMBA+Trademark+Guidelines
+4. http://www.arm.com/products/system-ip/amba/index.php?tab=AMBA+Trademark+Guidelines
 
-[(5)](=#fn5) http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
+5. http://www.altera.com/literature/manual/mnl_avalon_spec.pdf
 
-[(6)](=#fn6) http://www.altera.com/devices/processor/nios2/ni2-index.html
+6. http://www.altera.com/devices/processor/nios2/ni2-index.html
 
-[(7)](=#fn7) http://opencores.org/
+7. http://opencores.org/
 
-[(8)](=#fn8) https://en.wikipedia.org/wiki/CoreConnect
+8. https://en.wikipedia.org/wiki/CoreConnect
 
-[(9)](=#fn9) http://www.xilinx.com/products/intellectual-property/dr_pcentral_coreconnect.htm
+9. http://www.xilinx.com/products/intellectual-property/dr_pcentral_coreconnect.htm
 
-[(10)](=#fn10) http://www.xilinx.com/ipcenter/doc/ibm_click_core_connect_license.pdf
+10. http://www.xilinx.com/ipcenter/doc/ibm_click_core_connect_license.pdf
 
-[(11)](=#fn11) https://en.wikipedia.org/wiki/Open_Core_Protocol
+11. https://en.wikipedia.org/wiki/Open_Core_Protocol
 
-[(12)](=#fn12) https://en.wikipedia.org/wiki/Accellera
+12. https://en.wikipedia.org/wiki/Accellera
 
-[(13)](=#fn13) http://www.ocpip.org/
+13. http://www.ocpip.org/
 
-[(14)](=#fn14) http://www.ocpip.org/license_signup.php
+14. http://www.ocpip.org/license_signup.php
 
-[(15)](=#fn15) http://opencores.org/opencores,wishbone
+15. http://opencores.org/opencores,wishbone
 
-[(16)](=#fn16) https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
+16. https://en.wikipedia.org/wiki/Wishbone_(computer_bus)
 
-[(17)](=#fn17) http://openrisc.net/
+17. http://openrisc.net/
 
-[(18)](=#fn18) http://opencores.org/or1k/Main_Page
+18. http://opencores.org/or1k/Main_Page
 
 
 ## Copyright and License
diff --git a/pelican/content/Joachim Strömbergson.md b/pelican/content/Joachim Strömbergson.md
index 7fa6bb0..5a74548 100644
--- a/pelican/content/Joachim Strömbergson.md
+++ b/pelican/content/Joachim Strömbergson.md
@@ -35,9 +35,9 @@ Date: 2016-12-15 22:54
 We need to create an accelerator or possibly a complete implementation of the Curve25519 EC based DH-excgange.  We should be able to look at some previous work:
 
 
-* http://eprint.iacr.org/2013/375 - [NaCl]({filename}NaCl.md) on 8-Bit AVR Microcontrollers. Includes an iterative implementation of Curve25519
+* http://eprint.iacr.org/2013/375 - NaCl on 8-Bit AVR Microcontrollers. Includes an iterative implementation of Curve25519
 * http://cryptojedi.org/crypto/index.shtml - The code to the implementation
-* http://nacl.cr.yp.to/ - The main [NaCl]({filename}NaCl.md) library by DJB.
+* http://nacl.cr.yp.to/ - The main NaCl library by DJB.
 * http://cr.yp.to/ecdh/curve25519-20060209.pdf - The Curve25519 paper by DJB.
 
 
@@ -197,7 +197,7 @@ Technology
 - Toolchains and languages
     - SW
     - HW
-        - Verilog 2001, 2005, [SystemVerilog]({filename}SystemVerilog.md)
+        - Verilog 2001, 2005, SystemVerilog
         - Icarus, gplcver
         - Vendor specific
         - Validation of bitstream
@@ -223,7 +223,7 @@ Technology
 
 
 - Reuse of existing design, code?
-    - Cores - [OpenCores]({filename}OpenCores.md)
+    - Cores - OpenCores
         - OpenRISC
         - AES, SHA, RSA
     - SoftHSM - DNSSEC PKCS#11
@@ -331,7 +331,7 @@ Documentation
 -------------
 
 - Meetings
-    - Discussions, [MoMs]({filename}MoMs.md)
+    - Discussions, MoMs
     - Decisiona - motivation
 
 
diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md
index 1346494..78a0bcf 100644
--- a/pelican/content/OpenCryptoChip.md
+++ b/pelican/content/OpenCryptoChip.md
@@ -87,8 +87,8 @@ As a proof of concept, to validate as much as possible the assurance of the tool
 
 * [SUNET is sponsoring the first two development steps]({filename}SunetInitialDevelopment.md) currently being done.
 * [ Investigation and planning of a TRNG with entropy sources]({filename}TRNGDevelopment.md)
-* [Investigation of possible EDA tools and ways to do open and assured HW development"]({filename}EDAToolchainSurvey".md)
-* [Collection about side-channel attacks and detection, mitigation methods"]({filename}SideChannel".md)
+* [Investigation of possible EDA tools and ways to do open and assured HW development"]({filename}EDAToolchainSurvey.md)
+* [Collection about side-channel attacks and detection, mitigation methods]({filename}SideChannel.md)
 
 
 # v0.1 Major Sub-Projects
@@ -184,4 +184,4 @@ Here is a writeup on how to [setup and run coretest_hashes on the C5G board]({fi
 
 
 # Future Development
-The v0.1 version of [CrypTech]({filename}CrypTech.md) is not the last version nor the only possible version. The project for example consider possible [ASIC Implementations]({filename}ASICImplementations.md).
+The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible [ASIC Implementations]({filename}ASICImplementations.md).
diff --git a/pelican/content/PostAlphaPlan.md b/pelican/content/PostAlphaPlan.md
index 90cfa59..1d4e152 100644
--- a/pelican/content/PostAlphaPlan.md
+++ b/pelican/content/PostAlphaPlan.md
@@ -34,13 +34,13 @@ The software plan is divided into 3 parts: "now", "next week" and "next month".
 ### Now
 
 
-* CLI updates [but waiting on a BSD-friendly license](Done,)
-* rewrite keystore code to support larger keysizes and more slots [Done]
-* multi-core resource management [Done]
-* finish verilog EC point multiplier [Done]
+* CLI updates \[Done, but waiting on a BSD-friendly license\]
+* rewrite keystore code to support larger keysizes and more slots \[Done\]
+* multi-core resource management \[Done\]
+* finish verilog EC point multiplier \[Done\]
 * increase clock speed
-* openssl engine [Done]
-* debug log [done, nothing using it yet](Mechanism)
+* openssl engine \[Done\]
+* debug log \[Mechanism done, nothing using it yet\]
 * usb driver matching rev04 usb updates
 
 
@@ -48,12 +48,12 @@ The software plan is divided into 3 parts: "now", "next week" and "next month".
 
 
 * GOST drivers
-* key backup [Done]
+* key backup \[Done\]
 * SHA3
-* ECDSA verilog [Done]
+* ECDSA verilog \[Done\]
 * build system configuration management
 * real documentation: user, admin and dev manuals
-* Python RPC client [Done]
+* Python RPC client \[Done\]
 * set time and date from CLI
 
 
@@ -73,4 +73,4 @@ The software plan is divided into 3 parts: "now", "next week" and "next month".
 
 ### Eventually
 
-* Profiling [done](Mechanism)
+* Profiling \[Mechanism done\]
diff --git a/pelican/content/ProjectMetadata.md b/pelican/content/ProjectMetadata.md
index a8d7709..ac848ad 100644
--- a/pelican/content/ProjectMetadata.md
+++ b/pelican/content/ProjectMetadata.md
@@ -8,7 +8,7 @@ Date: 2016-12-15 22:43
 ## Project Logo Files
 
 * See "Attachments" at the bottom of this page
-* [PhotoFolder]({filename}PhotoFolder.md)
+* PhotoFolder
 
 
 == Meeting Presentations and Notes ==
diff --git a/pelican/content/QuickStart.md b/pelican/content/QuickStart.md
index 84f147d..e7f5477 100644
--- a/pelican/content/QuickStart.md
+++ b/pelican/content/QuickStart.md
@@ -28,4 +28,4 @@ The Alpha board currently ships with very old firmware, but you can [upgrade it
 
 # DNSSEC signing using OpenDNSSEC
 
-* [OpenDNSSEC](OpenDNSSEC)
+* [OpenDNSSEC]({filename}OpenDNSSEC.md)
diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md
index 1700e73..910e977 100644
--- a/pelican/content/RoughV1.md
+++ b/pelican/content/RoughV1.md
@@ -69,7 +69,7 @@ Verilog.
 ```
 
 
-* RSA 2048 & 4096 (move to blue later) [for Tor?](1024)
+* RSA 2048 & 4096 (move to blue later) \[ 1024 for Tor? \]
 * MACs: HMAC, 1305, uMAC
 * DH (move to blue later)
 * Device Activation, Move Authorization, Wiping
diff --git a/pelican/content/SideChannel.md b/pelican/content/SideChannel.md
index 3f170c4..9fd350e 100644
--- a/pelican/content/SideChannel.md
+++ b/pelican/content/SideChannel.md
@@ -5,7 +5,7 @@ Date: 2016-12-15 22:44
 
 # Side Channel Attacks
 
-Side Channel attacks on hardware are hard to avoid, detect and mitigate. But this should not stop us from trying. The [CrypTech]({filename}CrypTech.md) platform should be developed with side channel issues in mind. This page tries to collect information about relevant side channel attacks, mitigation strategies, side channel resistant design methods (blinding for example) and detection.
+Side Channel attacks on hardware are hard to avoid, detect and mitigate. But this should not stop us from trying. The CrypTech platform should be developed with side channel issues in mind. This page tries to collect information about relevant side channel attacks, mitigation strategies, side channel resistant design methods (blinding for example) and detection.
 
 
 * http://eprint.iacr.org/2013/579 "On Measurable Side-Channel Leaks inside ASIC Design Primitives"
diff --git a/pelican/content/StateOfPlay.md b/pelican/content/StateOfPlay.md
index 5c845cb..4d9be51 100644
--- a/pelican/content/StateOfPlay.md
+++ b/pelican/content/StateOfPlay.md
@@ -53,7 +53,7 @@ fits together.
 
 At this point I have figured out how to build two different FPGA
 images for the Novena PVT1.  In both cases, I'm using the Makefile
-rather than attempting to use the [XiLinx]({filename}XiLinx.md) GUI environment.
+rather than attempting to use the XiLinx GUI environment.
 
 
 * `core/novena` builds the current set of digest cores into a
diff --git a/pelican/content/UpgradeToKSNG.md b/pelican/content/UpgradeToKSNG.md
index 3ed1afb..bb4d02d 100644
--- a/pelican/content/UpgradeToKSNG.md
+++ b/pelican/content/UpgradeToKSNG.md
@@ -177,7 +177,7 @@ for it.
 
 The programmer is the important part, you can use any sort of cabling
 you like so long as it connects the right pins of the programmer to
-the corresponding pins on the Alpha; the [SparkFun]({filename}SparkFun.md) cable just happens
+the corresponding pins on the Alpha; the SparkFun cable just happens
 to be a tidy package which matches the relevant SWD headers.
 
 We'll include a more detailed description of the recovery process here
diff --git a/pelican/content/WhoWeAre.md b/pelican/content/WhoWeAre.md
index 52c5e53..0a05f78 100644
--- a/pelican/content/WhoWeAre.md
+++ b/pelican/content/WhoWeAre.md
@@ -12,7 +12,7 @@ But this is not an IETF, ISOC, ... project.  As the saying goes, we work for the
 
 Fredrik Thulin<br/>
 Jakob Schlyter<br/>
-[Joachim Strömbergson](Joachim Strömbergson)<br/>
+[Joachim Strömbergson]({filename}Joachim Strömbergson.md)<br/>
 Leif Johansson<br/>
 Linus Nordberg<br/>
 Lucy Lynch<br/>