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authorRob Austein <sra@hactrn.net>2021-02-15 22:29:56 +0000
committerRob Austein <sra@hactrn.net>2021-02-15 22:29:56 +0000
commit18fb1695b84248fc75ceb3569ff03cbeca51a620 (patch)
tree74e8c1473c11ca8db6f942d52acd5743c3e4d17c /pelican/content/StateOfPlay.md
parentdd255ef58a617214ea3ece613c417af1fc1549ec (diff)
Seriously rework link processing
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@@ -53,7 +53,7 @@ fits together.
At this point I have figured out how to build two different FPGA
images for the Novena PVT1. In both cases, I'm using the Makefile
-rather than attempting to use the XiLinx GUI environment.
+rather than attempting to use the [XiLinx](XiLinx.md) GUI environment.
* `core/novena` builds the current set of digest cores into a