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authorRob Austein <sra@hactrn.net>2021-02-15 00:04:31 +0000
committerRob Austein <sra@hactrn.net>2021-02-15 00:04:31 +0000
commit19904d9aca94471f60b49d7093908b21c4e926cc (patch)
treefe5b7b724c820adb6557ebded9b8940900bfd3f2 /pelican/content/RoughV1.md
parenta1d28e4a70e8ddaec4968766149d61efb76448bc (diff)
PKCS #11
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diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md
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@@ -87,12 +87,12 @@ Verilog.
* Interface to Red
- * PKCS!#8
- * PKCS!#11
+ * PKCS#8
+ * PKCS#11
* PGP Support
* X.509 and PGP
-* PKCS!#11 for POLA resistance
-* No PKCS!#10 because it will take a year
+* PKCS#11 for POLA resistance
+* No PKCS#10 because it will take a year
* Backup may be just dump/restore of the whole FPGA/CoreState