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author | Rob Austein <sra@hactrn.net> | 2021-02-14 23:00:42 +0000 |
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committer | Rob Austein <sra@hactrn.net> | 2021-02-14 23:00:42 +0000 |
commit | a1d28e4a70e8ddaec4968766149d61efb76448bc (patch) | |
tree | c21ce2c9932acd7d26bd5acb9edaac9794105a62 /pelican/content/EDAToolchainSurvey.md | |
parent | 8428fbcf08f34a3d6714484bf4445c5ec817354b (diff) |
Yet more links
Diffstat (limited to 'pelican/content/EDAToolchainSurvey.md')
-rw-r--r-- | pelican/content/EDAToolchainSurvey.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/pelican/content/EDAToolchainSurvey.md b/pelican/content/EDAToolchainSurvey.md index b54355a..cdb1e4d 100644 --- a/pelican/content/EDAToolchainSurvey.md +++ b/pelican/content/EDAToolchainSurvey.md @@ -13,7 +13,7 @@ The basic action flow is: Some tools and frameworks worth investigating are: -* ["OpTiMSoC"](http://www.optimsoc.org/index.html) - An open System on Chip (SoC) framework built around the OpenRISC CPU. -* ["Icarus Verilog"](http://iverilog.icarus.com/) - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog. -* ["gEDA"](http://www.geda-project.org/) - A project that aims at developing GNU based EDA tools. -* ["gplEDA"](http://www.gpleda.org/) - A collection of GPL licensed EDA tools. Points to gEDA. +* [OpTiMSoC](http://www.optimsoc.org/index.html) - An open System on Chip (SoC) framework built around the OpenRISC CPU. +* [Icarus Verilog](http://iverilog.icarus.com/) - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog. +* [gEDA](http://www.geda-project.org/) - A project that aims at developing GNU based EDA tools. +* [gplEDA](http://www.gpleda.org/) - A collection of GPL licensed EDA tools. Points to gEDA. |