linebreaks

8 files changed, 138 insertions, 67 deletions

diff --git a/markdown/AlphaBoardComponents.md b/markdown/AlphaBoardComponents.md
index ba8ba53..20b2ca5 100644
--- a/markdown/AlphaBoardComponents.md
+++ b/markdown/AlphaBoardComponents.md
@@ -1,17 +1,25 @@
 # CrypTech Alpha Board BOM and PCB design requirement sketch
-This document contains a list of component level description and requirements for the Crypteh Alpha board.[[BR]]
-The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.[[BR]]
+This document contains a list of component level description and requirements for the Crypteh Alpha board.  
+
+The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.  
+
 The block diagram for the Alpha board can be seen at: [wiki:Hardware]
 
-The Alpha board basically consists of three major sub systems:[[BR]]
-1. **The FPGA Sub System**[[BR]]
-   Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors.[[BR]]
+The Alpha board basically consists of three major sub systems:  
+
+1. **The FPGA Sub System**  
+
+   Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors.  
+
+
+2. **The CPU Sub System**  
 
-2. **The CPU Sub System**[[BR]]
    Talks to host systems and handles incoming commands. Basically implements the application interface.
-   Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards.[[BR]]
+   Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards.  
+
+
+3. **The Tamper Detect Sub System**  
 
-3. **The Tamper Detect Sub System**[[BR]]
    Responsible for implementing tamper detection and control/alarm as a separate functionality from the CPU.
    On the Alpha board this system is fairly simplistic. But we want to at least have a minor MCU that can run
    independently on battery power and control the Master Key Memory (MKM). detect external events and generate
@@ -37,8 +45,12 @@ Joachim Strömbergson, Fredrik Thulin
 ###  FPGA
 The board should be equipped with a Xilinx Artix-7 200T FPGA device, more specifically XC7A200T FBG484 speed grade -3.
 
-* [Xilinx Artix-7 XC7A200T FBG484.][[BR]](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html)
-* [Product family overview][[BR]](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf)
+* [Xilinx Artix-7 XC7A200T FBG484.](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html)  
+
+
+
+* [Product family overview](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf)  
+
 
 
 The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by XC7A100T and XC7A75T.
@@ -114,7 +126,8 @@ Suggested components for the MKM and the switch:
 
 * Memory: Microchip serial SRAM. 23A640, 8 kByte, 8-TSSOP or 8-SOIC
 
-[http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf][[BR]](http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf][[BR])
+[http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf](http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf)  
+
 
 
 * Quad 2-channel Analog Switch: ON Semi. MC14551B
@@ -184,8 +197,10 @@ The STM32 CPU supports two separate SDRAM banks. We use both of them with as big
 
 * Suggested chip: Microchip MCP79411 or MCP79412 connected to the CPU via I2C.
 
-  [http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411][[BR]](http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411][[BR])
-  [http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf][[BR]](http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf][[BR])
+  [http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411](http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411)  
+
+  [http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf](http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf)  
+
   This chip requires an external 32 kHz crystal.
 
 * Note: these chips contain per chip unique IDs as well as small EEPROM memory that can be memory protected.
diff --git a/markdown/AlphaBoardStrategy.md b/markdown/AlphaBoardStrategy.md
index e7f36a2..23c0b31 100644
--- a/markdown/AlphaBoardStrategy.md
+++ b/markdown/AlphaBoardStrategy.md
@@ -25,11 +25,13 @@ Develop a first, custom HSM board that can be used to support a first set of app
 
 ## Way forward
 
-We currently use the Novena as a dev-board. It has a ["Freescale i.MX6 CPU (ARM Cortex A9)"], and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA.[[BR]](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets)
+We currently use the Novena as a dev-board. It has a ["Freescale i.MX6 CPU (ARM Cortex A9)"](http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX6Q&tab=Documentation_Tab&pspll=1&SelectedAsset=Documentation&ProdMetaId=PID/DC/i.MX6Q&fromPSP=true&assetLockedForNavigation=true&componentId=2&leftNavCode=1&pageSize=25&Documentation=Documentation/00610Ksd1nd%60%60Data%20Sheets&fpsp=1&linkline=Data%20Sheets), and a Xilinx Spartan-6 LX45 CSG324-packaged FPGA.  
+
 
 We want to over-size rather than under-size the FPGA on the Alpha board. The biggest FPGA from Xilinx/Altera that does not require tools with a commercial license that we've found is the ​Xilinx Artix-7 XC7A200T FBG484.
 
-We've only considered ARM CPUs. Either about the size of Cortex M3 / M4 (or future M7) or Cortex A8 / A9.[[BR]]
+We've only considered ARM CPUs. Either about the size of Cortex M3 / M4 (or future M7) or Cortex A8 / A9.  
+
 A design with an A8/A9 turned out to be unattractive from a complexity and price point of view, so we're going to use one of the biggest M4 we could find. STM32F429.
 
 
@@ -46,12 +48,15 @@ We are currently using a Freescale proprietary interface called EIM between the
 
 ## Conclusion
 
-Use a high-end Cortex-M4 ARM.[[BR]]
+Use a high-end Cortex-M4 ARM.  
+
 There is a huge difference in complexity between M4 and A9, mainly because of the DDR3 memory used with A9. An M4 design will both be easier to design, cheaper to both design and build and will be fast enough for all our early use cases anyways.
 
 
-Do not use the exact same FPGA, as it is too small to fit everything we need.[[BR]]
+Do not use the exact same FPGA, as it is too small to fit everything we need.  
+
+
 
+Develop full schematics in-house.  
 
-Develop full schematics in-house.[[BR]]
 It turned out to be hard, costly or both, to outsource this part. We will probably spend less time developing the schematics ourselves than we would spend explaining what to develop to a third party.
diff --git a/markdown/Documents.md b/markdown/Documents.md
index 77593fd..94d19e1 100644
--- a/markdown/Documents.md
+++ b/markdown/Documents.md
@@ -9,7 +9,8 @@ Remember that links from this page to files in git repositories should use the "
 
 ```
 
-[RandomnessTesting Randomness Testing Tools][[BR]]
+[RandomnessTesting Randomness Testing Tools]  
+
 
 [AlphaBoardStrategy Alpha board strategy]
 
diff --git a/markdown/MailingLists.md b/markdown/MailingLists.md
index 95cb5cf..599f336 100644
--- a/markdown/MailingLists.md
+++ b/markdown/MailingLists.md
@@ -4,34 +4,49 @@
 
 The following lists are open to all:
 
-* Cryptech Project Announcements\\
+* Cryptech Project Announcements  
+
+
+  announce@cryptech.is  
+
+  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/announce)  
 
-  announce@cryptech.is\\
-  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/announce)\\
   [Announce List Archive](https://lists.cryptech.is/archives/announce/)
 
-* General technology and engineering list\\
+* General technology and engineering list  
+
+
+  tech@cryptech.is  
+
+  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/tech)  
 
-  tech@cryptech.is\\
-  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/tech)\\
   [Tech List Archive](https://lists.cryptech.is/archives/tech/)
 
-* Repository commit watch list (posting restricted)\\
+* Repository commit watch list (posting restricted)  
+
+
+  commit@cryptech.is  
+
+  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/commits)  
 
-  commit@cryptech.is\\
-  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/commits)\\
   [Commit List Archive](https://lists.cryptech.is/archives/commits)
 
 The following lists require approval for subscription:
 
-* Cryptech Project Core Team\\
+* Cryptech Project Core Team  
+
+
+  core@cryptech.is  
+
+  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/core)  
 
-  core@cryptech.is\\
-  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/core)\\
   [Core List Archive](https://lists.cryptech.is/archives/core/)
 
-* Finance, funding, administration\\
+* Finance, funding, administration  
+
+
+  org@cryptec.is  
+
+  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/org)  
 
-  org@cryptec.is\\
-  [Subscribe/Unsubscribe](https://lists.cryptech.is/listinfo/org)\\
   [Org List Archive](https://lists.cryptech.is/archives/org/)
diff --git a/markdown/OpenCryptoChip.md b/markdown/OpenCryptoChip.md
index 145ae07..ab250a3 100644
--- a/markdown/OpenCryptoChip.md
+++ b/markdown/OpenCryptoChip.md
@@ -3,11 +3,14 @@
 # An Open Crypto Chip
 
 ## The Layer Cake Architecture Picture
-\\
+  
+
 <img src="layer-cake.jpg">
 
-\\
-\\
+  
+
+  
+
 ## Use Cases
 
 * RPKI/DNSSEC Signing
@@ -63,8 +66,10 @@ We need to support key wrapping. Some pointers:
 
 # Rough Cut at v0.01 Proof of Concept Feature Set
 As a proof of concept, to validate as much as possible the assurance of the tools and methods, and as a demonstration of the project tools, team, and architecture, we have a [wiki:RoughV1 proposed version 0.01 product] as a proof of concept and a demonstration of the project tools, team, and architecture
-\\
-\\
+  
+
+  
+
 # Ongoing Decisions and Research
 
 * Security Target Description
@@ -76,8 +81,10 @@ As a proof of concept, to validate as much as possible the assurance of the tool
 * Prototyping Platform(s)
 * Documentation, Decision History, & Transparency
 
-\\
-\\
+  
+
+  
+
 
 # Ongoing Development
 
diff --git a/markdown/RelatedWork.md b/markdown/RelatedWork.md
index 8b48baf..221f614 100644
--- a/markdown/RelatedWork.md
+++ b/markdown/RelatedWork.md
@@ -1,8 +1,10 @@
 # Related Work
 
 ## Richard Lamb / ICANN
-[Presentation at ICANN](http://ccnso.icann.org/file/32383/download/37379)\\
-[Presentation at ICANN](http://ccnso.icann.org/file/40211/download/52359)\\
+[Presentation at ICANN](http://ccnso.icann.org/file/32383/download/37379)  
+
+[Presentation at ICANN](http://ccnso.icann.org/file/40211/download/52359)  
+
 "I wrote pkcs11 libraries and also have modified BIND that offloads full
 RRSIG calculation (including time) to board.  Clearly can use anything
 other than TPM to do RSA calculations."
@@ -15,7 +17,8 @@ other than TPM to do RSA calculations."
 
 
 ## Project Turris - CZNIC
-[Project Thuris Web Pages](http://www.turris.cz/en/)\\
+[Project Thuris Web Pages](http://www.turris.cz/en/)  
+
 Project Turris is a service helping to protect its user's home network
 with the help of a special router. It is a not-for-profit research
 project of CZ.NIC, z. s. p. o., the registry of the Czech national top
diff --git a/markdown/RoughV1.md b/markdown/RoughV1.md
index 95476aa..1c0ec56 100644
--- a/markdown/RoughV1.md
+++ b/markdown/RoughV1.md
@@ -20,12 +20,16 @@ Verilog.
 
 ## FPGA Overview
 <img src="HW_sketch_v0001.png">
-\\
-\\
+  
+
+  
+
 ## Sketch of TRNG Chain
 <img src="HW_RNG.png​">
-\\
-\\
+  
+
+  
+
 
 ## Off-FPGA
 
diff --git a/markdown/WhoWeAre.md b/markdown/WhoWeAre.md
index bed3562..1299661 100644
--- a/markdown/WhoWeAre.md
+++ b/markdown/WhoWeAre.md
@@ -6,35 +6,56 @@ But this is not an IETF, ISOC, ... project.  As the saying goes, we work for the
 
 ## Tech Core
 
-Fredrik Thulin\\
-Jakob Schlyter\\
-[[Joachim Strömbergson]]\\
-Leif Johansson\\
-Linus Nordberg\\
-Lucy Lynch\\
-Patrik Wallström \\
-Павел Шатов (Pavel Shatov)\\
-Peter Stuge\\
-[Randy Bush](https://psg.com/~randy)\\
-[Austein]]([https://www.hactrn.net/sra/|Rob)\\
-Steven Bellovin\\
-Basil Dolmatov\\
+Fredrik Thulin  
+
+Jakob Schlyter  
+
+[[Joachim Strömbergson]]  
+
+Leif Johansson  
+
+Linus Nordberg  
+
+Lucy Lynch  
+
+Patrik Wallström   
+
+Павел Шатов (Pavel Shatov)  
+
+Peter Stuge  
+
+[Randy Bush](https://psg.com/~randy)  
+
+[Austein]]([https://www.hactrn.net/sra/|Rob)  
+
+Steven Bellovin  
+
+Basil Dolmatov  
+
 
 ```#!comment == Technical Help ==
 Bart Preneel ![0]\\
+
 Tero Kivinenv ![0]\\
+
 ```
 
 ## IETF Help
 
-Russ Housley\\
-Sean Turner\\
-Stephen Farrell\\
+Russ Housley  
+
+Sean Turner  
+
+Stephen Farrell  
+
 
 ## Coordination
 
-Leif Johansson - Administration\\
-Randy Bush - Technical\\
-Russ Housley / Lynn StAmour - Finding Funding\\
+Leif Johansson - Administration  
+
+Randy Bush - Technical  
+
+Russ Housley / Lynn StAmour - Finding Funding  
+
 
 ------