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| author | Rob Austein <sra@hactrn.net> | 2021-02-14 01:56:47 +0000 |
|---|---|---|
| committer | Rob Austein <sra@hactrn.net> | 2021-02-14 01:56:47 +0000 |
| commit | e6fc8bed7e3a5e80882781359543c99d7de018fe (patch) | |
| tree | 877afc87c74ce0b9666852c5cb712e101bf51888 /markdown/RoughV1.md | |
| parent | b58c60bcc4a6f3d3ccf4194ef862a808fdc3313b (diff) | |
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Diffstat (limited to 'markdown/RoughV1.md')
| -rw-r--r-- | markdown/RoughV1.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/markdown/RoughV1.md b/markdown/RoughV1.md index 1891975..95476aa 100644 --- a/markdown/RoughV1.md +++ b/markdown/RoughV1.md @@ -19,11 +19,11 @@ source out of the can. for v.2 (or whatever) we would move it down to the FPGA Verilog. ## FPGA Overview -[[Image(HW_sketch_v0001.png)]] +<img src="HW_sketch_v0001.png"> \\ \\ ## Sketch of TRNG Chain -[[Image(HW_RNG.png)]] +<img src="HW_RNG.png"> \\ \\ |