A lot of minor cleanup

1 files changed, 12 insertions, 3 deletions

diff --git a/content/EDAToolchainSurvey.md b/content/EDAToolchainSurvey.md
index b8632a6..287d5af 100644
--- a/content/EDAToolchainSurvey.md
+++ b/content/EDAToolchainSurvey.md
@@ -1,8 +1,17 @@
-Title: EDAToolchainSurvey
-Author: trac
+Title: EDA Toolchain Survey
 Date: 2016-12-15 22:43
 
-The major issue is finding tools that allows a designer, user to verify that the RTL source code (in Verilog or VHDL) matches what is generated at the physical level. As part of the project we need to investigate the current status of open tools in the toolchain for implementation and verification of hardware. This includes RTL simulation, synthesis, place & route, netlist verification, timing analysis and configuration file generation and analysis. (This implies that the target is an FPGA.). If there are no open tools we need to find ways of verifying pre- and post-functionality to check that the black box tool does not alter (subvert) the design in ways not intended.
+The major issue is finding tools that allows a designer, user to
+verify that the RTL source code (in Verilog or VHDL) matches what is
+generated at the physical level. As part of the project we need to
+investigate the current status of open tools in the toolchain for
+implementation and verification of hardware. This includes RTL
+simulation, synthesis, place & route, netlist verification, timing
+analysis and configuration file generation and analysis. (This implies
+that the target is an FPGA.). If there are no open tools we need to
+find ways of verifying pre- and post-functionality to check that the
+black box tool does not alter (subvert) the design in ways not
+intended.
 
 The basic action flow is: