blob: 02cd5287f44475acdbce538194232a9bff8dd23f (
plain) (
tree)
|
|
{{{
#!htmlcomment
This page is maintained automatically by a script. Don't modify this page by hand,
your changes will just be overwritten the next time the script runs. Talk to your
Friendly Neighborhood Repository Maintainer if you need to change something here.
}}}
{{{
#!html
<h1>coretest_fpga_entropy</h1>
<p>Coretest system for testing FPGA based entropy source.</p>
<h2>Introduction</h2>
<p>This project is a coretest system dedicated to test entropy sources
within a FPGA device. The specific entropy source is based on a digital
oscillator design by Bernd Paysan. In this entropy source, we use six
instances with different frequencies. The oscillator outputs are
combined to generate a bit value. 32 bit values are combined to create a
random word.</p>
<p>The system uses the coretest module to read and write 32-bit data to
core, In this case it allows a caller to read generated random 16-bit
values from the entropy source. The 16 bit data is in the LSB of the
word.</p>
<p>The completc system contains a UART core for external access. The
project contains pin assignments etc to implement the system on a
TerasIC C5G board.</p>
<h2>Implementation details.</h2>
<p>This FPGA system consists of the following components:</p>
<ul>
<li>The FPGA entropy source core</li>
<li>The UART core</li>
<li>The coretest core</li>
</ul>
<p>There are pin assignments and clock defines for the TerasIC C5G board.</p>
}}}
[[RepositoryIndex(format=table,glob=test/coretest_fpga_entropy)]]
|| Clone `https://git.cryptech.is/test/coretest_fpga_entropy.git` ||
|
