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<h1>coretest_bpaysan_entropy</h1>
<p>Coretest system for testing the FPGA based entropy source developed by Bernd Paysan.</p>
<h2>Introduction</h2>
<p>This project is a coretest system dedicated to test entropy sources
within a FPGA device. The specific entropy source has ben designed by
Bernd Paysan.</p>
<p>The entropy source used two sets of 16 free running digital oscillators
that are interconnected.</p>
<p>The system uses the coretest module to read and write 32-bit data to
core, In this case it allows a caller to read generated random 16-bit
values from the entropy source. The 16 bit data is in the LSB of the
word.</p>
<p>The completc system contains a UART core for external access. The
project contains pin assignments etc to implement the system on a
TerasIC C5G board.</p>
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[[RepositoryIndex(format=table,glob=test/coretest_bp_entropy)]]
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