Title: Post Alpha Plan
Author: Paul Selkirk
Date: 2016-12-15 22:44
Modified: 2017-05-16 14:53
The core dev team had a design meeting in Berlin after the alpha workshop. We came up with a plan for the hardware and the software work for the next few months:
This is targeted for the mid-flight revision in the 50 board order from propoint. For practical reasons, we should limit ourselves to bugfixes and other "low risk" changes for this release.
- On-board battery (super-cap, long battery life etc, battery outside the tamper boundary etc)
- Next generation USB based on Stuges daughter board work
- Support higher clock speeds
- Proposed: pull out 2 more UARTS from the STM32 to support memory-card readers and pin-entry devices
- Power instrumentation
- EMC
- Tamper revisions??
The software plan is divided into 3 parts: "now", "next week" and "next month". These are labels, not a time frame. The "now" list represents stuff that is currently seeing active work. We move stuff from "next week" to "now" and from "next month" to "next week" as part of our planning process (at the engineering calls).
- CLI updates [Done, but waiting on a BSD-friendly license]
- rewrite keystore code to support larger keysizes and more slots [Done]
- multi-core resource management [Done]
- finish verilog EC point multiplier [Done]
- increase clock speed
- openssl engine [Done]
- debug log [Mechanism done, nothing using it yet]
- usb driver matching rev04 usb updates
- GOST drivers
- key backup [Done]
- SHA3
- ECDSA verilog [Done]
- build system configuration management
- real documentation: user, admin and dev manuals
- Python RPC client [Done]
- set time and date from CLI
- 25519 verilog
- design papers
- doxygen
- m of n
- notify ARM and FPGA of tamper events
- secure channel
- ECDH
- AES drivers
- audit logging
- Profiling [Mechanism done]
