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{{{
#!htmlcomment

This page is maintained automatically by a script.  Don't modify this page by hand,
your changes will just be overwritten the next time the script runs.  Talk to your
Friendly Neighborhood Repository Maintainer if you need to change something here.

}}}

{{{
#!html
<h1>sha1</h1>

<h2>Introduction</h2>

<p>Verilog implementation of the SHA-1 cryptgraphic hash function. The
functionality follows the specification in NIST FIPS 180-4.</p>

<p>The sha1 design is divided into the following sections.</p>

<ul>
<li>src/rtl - RTL source files</li>
<li>src/tb  - Testbenches for the RTL files</li>
<li>src/model/python - Functional model written in python</li>
<li>doc/ - documentation (currently not done.)</li>
<li>toolruns/ - Where tools are supposed to be run. Includes a Makefile
for building and simulating the design using <a href="http://iverilog.icarus.com/">Icarus
Verilog</a>.</li>
</ul>

<p>The actual core consists of the following RTL files:</p>

<ul>
<li>sha1.v</li>
<li>sha1_core.v</li>
<li>sha1_w_mem.v</li>
</ul>

<p>The main core functionality is in the sha1_core file. The file
sha1_w_mem contains the message block memory W (see FIPS 180-4).
The top level entity is called sha1_core. The sha1_core module has wide
interfaces (512 bit block input, 160 bit digest). In order to make it
usable you probably want to wrap the core with a bus interface.</p>

<p>The file sha1.v contains a top level wrapper that provides a simple
interface with 32-bit data access . This interface contains mesage block
and digest registers to allow a host to load the next block while the
current block is being processed.</p>

<h2>API</h2>

<p>The following list contains the address map for all registers
implemented by the sha1 top level wrapper:</p>

<table>
<thead>
<tr>
  <th>address</th>
  <th>name</th>
  <th>access</th>
  <th>description</th>
</tr>
</thead>
<tbody>
<tr>
  <td>0x00</td>
  <td>name0</td>
  <td>R</td>
  <td>"SHA1"</td>
</tr>
<tr>
  <td>0x01</td>
  <td>name1</td>
  <td>R</td>
  <td>"    "</td>
</tr>
<tr>
  <td>0x02</td>
  <td>version</td>
  <td>R</td>
  <td>"0.50"</td>
</tr>
<tr>
  <td></td>
</tr>
<tr>
  <td>0x08</td>
  <td>control</td>
  <td>R/W</td>
  <td>Control of core. Bit 0: init, Bit 1: next</td>
</tr>
<tr>
  <td>0x09</td>
  <td>status</td>
  <td>R/W</td>
  <td>Status of core. Bit 0: Ready, Bit 1: valid data</td>
</tr>
<tr>
  <td></td>
</tr>
<tr>
  <td>0x10</td>
  <td>block0</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x11</td>
  <td>block1</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x12</td>
  <td>block2</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x13</td>
  <td>block3</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x14</td>
  <td>block4</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x15</td>
  <td>block5</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x16</td>
  <td>block6</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x17</td>
  <td>block7</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x18</td>
  <td>block8</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x19</td>
  <td>block9</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1a</td>
  <td>block10</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1b</td>
  <td>block11</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1c</td>
  <td>block12</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1d</td>
  <td>block13</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1e</td>
  <td>block14</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td>0x1f</td>
  <td>block15</td>
  <td>R/W</td>
  <td>data block register</td>
</tr>
<tr>
  <td></td>
</tr>
<tr>
  <td>0x20</td>
  <td>digest0</td>
  <td>R/W</td>
  <td>digest register</td>
</tr>
<tr>
  <td>0x21</td>
  <td>digest1</td>
  <td>R/W</td>
  <td>digest register</td>
</tr>
<tr>
  <td>0x22</td>
  <td>digest2</td>
  <td>R/W</td>
  <td>digest register</td>
</tr>
<tr>
  <td>0x23</td>
  <td>digest3</td>
  <td>R/W</td>
  <td>digest register</td>
</tr>
<tr>
  <td>0x24</td>
  <td>digest4</td>
  <td>R/W</td>
  <td>digest register</td>
</tr>
</tbody>
</table>

<h2>Implementation details</h2>

<p>The implementation is iterative with one cycle/round. The initialization
takes one cycle. The W memory is based around a sliding window of 16
32-bit registers that are updated in sync with the round processing. The
total latency/message block is 82 cycles.</p>

<p>All registers have asynchronous reset.</p>

<p>The design has been implemented and tested on TerasIC DE0-Nano and C5G
FPGA boards.</p>

<h2>Status</h2>

<p>The design has been implemented and extensively been tested on TerasIC
DE0-Nano and C5G FPGA boards. The core has also been tested using SW
running on The Novena CPU talking to the core in the Xilinx Spartan-6
FPGA.</p>

<h2>FPGA-results</h2>

<h3>Altera Cyclone FPGAs</h3>

<p>Implementation results using Altera Quartus-II 13.1.</p>

<p><strong><em>Altera Cyclone IV E</em></strong></p>

<ul>
<li>EP4CE6F17C6</li>
<li>2913 LEs</li>
<li>1527 regs</li>
<li>107 MHz</li>
</ul>

<p><strong><em>Altera Cyclone IV GX</em></strong></p>

<ul>
<li>EP4CGX22CF19C6</li>
<li>2814 LEs</li>
<li>1527 regs</li>
<li>105 MHz</li>
</ul>

<p><strong><em>Altera Cyclone V</em></strong></p>

<ul>
<li>5CGXFC7C7F23C8</li>
<li>1124 ALMs</li>
<li>1527 regs</li>
<li>104 MHz</li>
</ul>

<h3>Xilinx FPGAs</h3>

<p>Implementation results using ISE 14.7.</p>

<p><em>* Xilinx Spartan-6 *</em></p>

<ul>
<li>xc6slx45-3csg324</li>
<li>1589 LUTs</li>
<li>564 Slices</li>
<li>1592 regs</li>
<li>100 MHz</li>
</ul>

<h2>TODO</h2>

<ul>
<li>Documentation</li>
</ul>
}}}

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