blob: 6bfec8ef87073c4153d1cc7baf51b2bda9bcd3b6 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
{{{
#!htmlcomment
This page is maintained automatically by a script. Don't modify this page by hand,
your changes will just be overwritten the next time the script runs. Talk to your
Friendly Neighborhood Repository Maintainer if you need to change something here.
}}}
{{{
#!html
<h1>uart</h1>
<p>A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.</p>
<p>This UART used to be in coretest, but has been moved out as a separate
project.</p>
<p>The current implementation supports the ability to set the bit rate as
well as number of data- and stop bits by writing to control addresses
via the control interface.</p>
}}}
[[RepositoryIndex(format=table,glob=core/comm/uart)]]
|| Clone `https://git.cryptech.is/core/comm/uart.git` ||
|
