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diff --git a/pelican/content/RoughV1.md b/pelican/content/RoughV1.md
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@@ -19,13 +19,13 @@ source out of the can. for v.2 (or whatever) we would move it down to the FPGA
Verilog.
## FPGA Overview
-<img src="HW_sketch_v0001.png">
+![HW_sketch_v0001.png]({attach}RoughV1/HW_sketch_v0001.png)
## Sketch of TRNG Chain
-<img src="HW_RNG.png​">
+![HW_RNG.png]({attach}RoughV1/HW_RNG.png)