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Diffstat (limited to 'pelican/content/OpenCryptoChip.md')
| -rw-r--r-- | pelican/content/OpenCryptoChip.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/pelican/content/OpenCryptoChip.md b/pelican/content/OpenCryptoChip.md index ac91cf2..397e14e 100644 --- a/pelican/content/OpenCryptoChip.md +++ b/pelican/content/OpenCryptoChip.md @@ -91,8 +91,8 @@ As a proof of concept, to validate as much as possible the assurance of the tool # Ongoing Development -* ["SUNET is sponsoring the first two development steps"](SunetInitialDevelopment) currently being done. -* [" Investigation and planning of a TRNG with entropy sources"](TRNGDevelopment) +* [SUNET is sponsoring the first two development steps](SunetInitialDevelopment) currently being done. +* [ Investigation and planning of a TRNG with entropy sources](TRNGDevelopment) * [Investigation of possible EDA tools and ways to do open and assured HW development"](EDAToolchainSurvey") * [Collection about side-channel attacks and detection, mitigation methods"](SideChannel") @@ -114,7 +114,7 @@ As a proof of concept, to validate as much as possible the assurance of the tool * TerasIC C5G Cyclone 5 GX Starter Kit. Includes an Altera C5GX FPGA. This board is used for core, subsystem development and verification. Info, documentation and ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830 -Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](CoretestHashesC5G). +Here is a writeup on how to [setup and run coretest_hashes on the C5G board](CoretestHashesC5G). * TerasIC DE0-Nano board. This tiny, USB powered board is used for core development and verification. Info, documentation, resources, ordering of the TerasIC board can be found here: http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593 @@ -128,7 +128,7 @@ Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](C * Research * Select -* ["On-chip Interconnect Standards"](InterconnectStandards) to use. +* [On-chip Interconnect Standards](InterconnectStandards) to use. ## Methods and Validation @@ -190,4 +190,4 @@ Here is a writeup on how to ["setup and run coretest_hashes on the C5G board"](C # Future Development -The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible ["ASIC Implementations"](ASICImplementations). +The v0.1 version of CrypTech is not the last version nor the only possible version. The project for example consider possible [ASIC Implementations](ASICImplementations). |