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Diffstat (limited to 'pelican/content/AlphaBoardComponents.md')
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1 files changed, 14 insertions, 31 deletions
diff --git a/pelican/content/AlphaBoardComponents.md b/pelican/content/AlphaBoardComponents.md index 2e005a0..39eb30e 100644 --- a/pelican/content/AlphaBoardComponents.md +++ b/pelican/content/AlphaBoardComponents.md @@ -3,27 +3,19 @@ Author: trac Date: 2016-12-15 22:43 # CrypTech Alpha Board BOM and PCB design requirement sketch -This document contains a list of component level description and requirements for the Crypteh Alpha board. - -The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed. - +This document contains a list of component level description and requirements for the Crypteh Alpha board.<br/> +The document is to be used as a BOM (Bill Of Materials) and PCB design requirement description for discussing with PCB designers on what we want to have designed.<br/> The block diagram for the Alpha board can be seen at: [Hardware]({filename}Hardware.md) -The Alpha board basically consists of three major sub systems: - -1. **The FPGA Sub System** - - Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors. - - -2. **The CPU Sub System** +The Alpha board basically consists of three major sub systems:<br/> +1. **The FPGA Sub System**<br/> + Used to implement CrypTech crypto/security cores accessible by the CPU as coprocessors.<br/> +2. **The CPU Sub System**<br/> Talks to host systems and handles incoming commands. Basically implements the application interface. - Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards. - - -3. **The Tamper Detect Sub System** + Controls the FPGA Sub System. The CPU Sub System is heavily inspired/based on the CPU parts of the Novena and the iMX6 Rex boards.<br/> +3. **The Tamper Detect Sub System**<br/> Responsible for implementing tamper detection and control/alarm as a separate functionality from the CPU. On the Alpha board this system is fairly simplistic. But we want to at least have a minor MCU that can run independently on battery power and control the Master Key Memory (MKM). detect external events and generate @@ -49,12 +41,8 @@ Joachim Strömbergson, Fredrik Thulin ### FPGA The board should be equipped with a Xilinx Artix-7 200T FPGA device, more specifically XC7A200T FBG484 speed grade -3. -* [Xilinx Artix-7 XC7A200T FBG484.](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html) - - - -* [Product family overview](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf) - +* [Xilinx Artix-7 XC7A200T FBG484.](http://www.xilinx.com/products/silicon-devices/fpga/artix-7.html)<br/> +* [Product family overview](http://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf)<br/> The FPGA pad layout should be compatible with the Xilinx Artix-7 FGG484 used by XC7A100T and XC7A75T. @@ -128,8 +116,7 @@ Suggested components for the MKM and the switch: * Memory: Microchip serial SRAM. 23A640, 8 kByte, 8-TSSOP or 8-SOIC -<http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf> - +<http://ww1.microchip.com/downloads/en/DeviceDoc/22127a.pdf><br/> * Quad 2-channel Analog Switch: ON Semi. MC14551B @@ -139,7 +126,7 @@ Suggested components for the MKM and the switch: ### Entropy Sources -* The avalanche noise entropy source should be implemented according to [existing schematics]({attach}AlphaBoardComponents/alpha_board_noise_source.pdf). +* The avalanche noise entropy source should be implemented according to [existing schematics]({attach}/AlphaBoardComponents/alpha_board_noise_source.pdf). * The noise source should have a shielding can and suitable ground plane etc. to keep radiation of entropy bits as low as possible. * The "12-15v stable" VCC should be controllable by the FPGA (enable/disable controlled by output pin on FPGA) to increase life time of components. Power requirements for this VCC is < 100 mA (needs measuring, but probably < 50 mA). @@ -196,13 +183,9 @@ The STM32 CPU supports two separate SDRAM banks. We use both of them with as big * Battery backed RTC with calendar/date information. Connected to the CPU via serial, SPI or other interface. * Suggested chip: Microchip MCP79411 or MCP79412 connected to the CPU via I2C. - <http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411> - - - <http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf> - + <http://www.microchip.com/wwwproducts/Devices.aspx?product=MCP79411><br/> + <http://ww1.microchip.com/downloads/en/DeviceDoc/20002266G.pdf><br/> This chip requires an external 32 kHz crystal. - * Note: these chips contain per chip unique IDs as well as small EEPROM memory that can be memory protected. |