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Diffstat (limited to 'pelican/content/ASICImplementations.md')
| -rw-r--r-- | pelican/content/ASICImplementations.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/pelican/content/ASICImplementations.md b/pelican/content/ASICImplementations.md index f3ce441..ba997c7 100644 --- a/pelican/content/ASICImplementations.md +++ b/pelican/content/ASICImplementations.md @@ -23,7 +23,7 @@ features from IEEE 1364-2001 (aka Verilog 2001). All RTL code is divided into modules that contain one process for register updates and reset (*reg_update*), one or more combinational processes for datapath and support logic such as counters. Finally if needed, each module has a separate process that implements the logic for the final state machine that controls the behaviour of the module. -All cores are divided into a core, for example *sha256_core.v* and a number of submodules the core instantiates. The core provides raw, wide ports (256 bit wide key for AES for example) that is not suitable to use in a stand alone system. Instead each core comes with a top level wrapper, for example *sha256.v*. This top level wrapper contains all registers and logic needed to provide all functionality of the core via a simple 32-bit memory like interface. If the core is going to be used as a tightly integrated submodule, the wrapper can be discarded. Similarly, if the core is going to be used in a bus system that use a specific bus standard such as AMBA AHB, [CoreConnect]({filename}CoreConnect.md) or WISHBONE, only the top level wrapper will be needed to be replaced or modified to match the desired bus standard. +All cores are divided into a core, for example *sha256_core.v* and a number of submodules the core instantiates. The core provides raw, wide ports (256 bit wide key for AES for example) that is not suitable to use in a stand alone system. Instead each core comes with a top level wrapper, for example *sha256.v*. This top level wrapper contains all registers and logic needed to provide all functionality of the core via a simple 32-bit memory like interface. If the core is going to be used as a tightly integrated submodule, the wrapper can be discarded. Similarly, if the core is going to be used in a bus system that use a specific bus standard such as AMBA AHB, CoreConnect or WISHBONE, only the top level wrapper will be needed to be replaced or modified to match the desired bus standard. The RTL code does not explicitly instantiate any hard macros such as memories, multipliers, etc. Instead all such functions are left to the |