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@@ -19,11 +19,11 @@ source out of the can. for v.2 (or whatever) we would move it down to the FPGA
Verilog.
## FPGA Overview
-[[Image(HW_sketch_v0001.png)]]
+<img src="HW_sketch_v0001.png">
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## Sketch of TRNG Chain
-[[Image(HW_RNG.png​)]]
+<img src="HW_RNG.png​">
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