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+**Note: this page has been replaced by wiki:EDAToolchainSurvey**
+
+The major issue is finding tools that allows a designer, user to verify that the RTL source code (in Verilog or VHDL) matches what is generated at the physical level. As part of the project we need to investigate the current status of open tools in the toolchain for implementation and verification of hardware. This includes RTL simulation, synthesis, place & route, netlist verification, timing analysis and configuration file generation and analysis. (This implies that the target is an FPGA.). If there are no open tools we need to find ways of verifying pre- and post-functionality to check that the black box tool does not alter (subvert) the design in ways not intended.
+
+The basic action flow is:
+
+* Finding open EDA tools and assess their status
+* Settling for Closed
+* Strategy to Develop Trust in Tools
+* Validation Methods for Output
+
+
+Some tools and frameworks worth investigating are:
+
+* ["OpTiMSoC"](http://www.optimsoc.org/index.html) - An open System on Chip (SoC) framework built around the OpenRISC CPU.
+* ["Icarus Verilog"](http://iverilog.icarus.com/) - An open Verilog event driven simulator that supports Verilog 2001, 2005 and SystemVerilog.
+* ["gEDA"](http://www.geda-project.org/) - A project that aims at developing GNU based EDA tools.
+* ["gplEDA"](http://www.gpleda.org/) - A collection of GPL licensed EDA tools. Points to gEDA.