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-rw-r--r--markdown/CoretestHashesC5G.md4
1 files changed, 2 insertions, 2 deletions
diff --git a/markdown/CoretestHashesC5G.md b/markdown/CoretestHashesC5G.md
index 7cc2e30..6d98aea 100644
--- a/markdown/CoretestHashesC5G.md
+++ b/markdown/CoretestHashesC5G.md
@@ -19,7 +19,7 @@ The test setup consists of:
- The TerasIC Cyclone 5 GX Starter Kit (C5G) board.
-[[Image(http://www.terasic.com.tw/attachment/archive/830/image/image_74_thumb.jpg)]]
+<img src="http://www.terasic.com.tw/attachment/archive/830/image/image_74_thumb.jpg">
*The TerasIC Cyclone 5 GX Starter Kit board.*
@@ -57,7 +57,7 @@ interface connected to a FPGA device. The subsystem consists of:
well as connecting the rxd and txd ports on the uart to external pins as well as clk and reset. This core repo also contains the Python command line program hash_tester we will be using to talk to coretester and perform tests of the sha1 and sha256 cores.
-[[Image(coretest_hashes.png)]]
+<img src="coretest_hashes.png">
*The coretest_hashes subsystem with sha1 and sha256 cores. The system is connected to a host computer via a serial interface.*